151 Commits

Author	SHA1	Message	Date
Alex Forencich	6cb5297e28	Fix TDMA BER pipeline register	2022-03-17 13:28:41 -07:00
Alex Forencich	1291d7b1b7	Add pipeline registers to TDMA BER modules	2022-03-15 17:40:27 -07:00
Alex Forencich	d9e79c9923	Rename cores to match transceiver type	2022-03-03 22:41:34 -08:00
Alex Forencich	90d28ec9a2	Add common 10G PHY + GTH/GTY transceiver wrapper module	2022-03-02 17:28:40 -08:00
Alex Forencich	614b391c48	Add DRP register block	2022-02-21 23:20:54 -08:00
Alex Forencich	65fbad93ca	Fix parameter defaults	2022-02-20 00:13:35 -08:00
Alex Forencich	3997e0d95b	Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter	2022-02-15 18:01:43 -08:00
Alex Forencich	66708ed6ff	Add some more parameter checks	2022-02-14 00:41:28 -08:00
Alex Forencich	627ac359d5	Add layer 2 ingress/egress modules	2022-02-13 23:09:41 -08:00
Alex Forencich	01f0631ddb	Update parameters	2022-02-11 22:04:04 -08:00
Alex Forencich	b7bc240aa6	Add JTAG and GPIO passthroughs to application section	2022-01-27 23:06:05 -08:00
Alex Forencich	36bd1f78b0	Add missing parameter connection in rx_fifo	2022-01-26 09:44:35 -08:00
Alex Forencich	137a6778da	Combine interface control blocks	2022-01-15 21:53:13 -08:00
Alex Forencich	ddd7e639da	Add tdest register to scheduler blocks	2021-12-31 17:02:59 -08:00
Alex Forencich	335a5e890b	Initial implementation of shared interface datapath	2021-12-31 14:33:31 -08:00
Alex Forencich	ce21774f06	Register space reorganization	2021-12-29 22:31:46 -08:00
Alex Forencich	6163efa0b8	Add output pipeline stage to descriptor FIFOs	2021-12-29 14:30:05 -08:00
Ulrich Langenbach	0560f98e79	support more than 4k queues (workaround quartus loop iteration limit)	2021-12-16 12:09:39 -08:00
Alex Forencich	540e7eb1de	Fix offset	2021-12-02 16:46:35 -08:00
Alex Forencich	089c405c4f	Fix clock connections	2021-11-30 16:39:27 -08:00
Alex Forencich	720a06ca8b	Update mux instances	2021-11-30 15:36:24 -08:00
Alex Forencich	639117e53f	Adjust clock connections to improve connection to testbench	2021-11-30 00:16:47 -08:00
Alex Forencich	2aa9158d5c	Limit scheduler pipeline to a single AXI lite operation	2021-11-19 16:29:16 -08:00
Alex Forencich	74f4c6fc2d	Support using separate clock for PTP timestamps on RX path	2021-11-18 23:56:51 -08:00
Alex Forencich	605965fec9	Add mqnic core logic module for AXI	2021-11-17 18:16:40 -08:00
Alex Forencich	bd8a0513ed	Add mqnic core logic for Stratix 10 GX/SX/TX/MX	2021-11-07 13:28:12 -08:00
Alex Forencich	7ab18f8602	Increase event FIFO depth	2021-11-06 16:14:49 -07:00
Alex Forencich	fb0f6f67f7	Remove debug code	2021-11-06 16:14:32 -07:00
Alex Forencich	f8a24d1c46	Add attributes to RAMs for proper synthesis in Quartus	2021-11-06 16:14:22 -07:00
Alex Forencich	aa89471cca	Add bus_num port to mqnic_core_pcie	2021-11-03 21:40:19 -07:00
Alex Forencich	7ac4797336	Add default_nettype none and resetall directives	2021-10-20 21:53:39 -07:00
Alex Forencich	607257d7bb	Fix connections	2021-10-20 20:43:11 -07:00
Alex Forencich	2c038c9b7b	Update FIFO instance	2021-10-13 16:44:05 -07:00
Alex Forencich	ec89492d24	Fix control register addressing bug	2021-09-11 00:49:48 -07:00
Alex Forencich	d24c53a2ad	Add application section	2021-09-09 16:01:26 -07:00
Alex Forencich	371717b854	Add block names	2021-09-09 14:12:41 -07:00
Alex Forencich	c920272e84	Use interface address widths directly instead of BAR size parameters	2021-09-08 14:51:18 -07:00
Alex Forencich	cef144e376	Expose DMA_LEN_WIDTH and DMA_TAG_WIDTH parameters	2021-09-08 00:18:11 -07:00
Alex Forencich	c00a53155d	Fix alignment	2021-09-07 01:38:09 -07:00
Alex Forencich	bdd2312ecc	More descriptive parameter and signal names for AXI lite control connections	2021-09-07 01:35:15 -07:00
Alex Forencich	8cf16c182b	More descriptive parameter names (SYNC instead of INT)	2021-09-07 01:29:35 -07:00
Alex Forencich	15dec9458a	Add statistics counter subsystem	2021-09-05 23:03:22 -07:00
Alex Forencich	9ccd43d470	Add statistics collection modules	2021-09-05 18:28:37 -07:00
Alex Forencich	5d760851ac	Limit queue manager pipelines to a single AXI lite operation	2021-09-05 12:46:56 -07:00
Alex Forencich	ef00d5ccfd	Add parameters for FIFO output pipeline register depth	2021-09-02 14:45:18 -07:00
Alex Forencich	de869347cd	Register interrupt signal	2021-09-01 13:14:02 -07:00
Alex Forencich	df9523011c	Normalize instance names	2021-09-01 02:14:53 -07:00
Alex Forencich	37a558e4f6	Add pipeline FIFOs	2021-08-31 22:30:45 -07:00
Alex Forencich	a5519cd607	Default to US+ configuration	2021-08-31 18:57:32 -07:00
Alex Forencich	bdbdc11841	Initial commit of core logic	2021-08-31 18:42:19 -07:00