Alex Forencich
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bed12ee774
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Consolidate CQs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-10 17:52:34 -07:00 |
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Alex Forencich
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448fa8eb4c
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Use SPDX
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-06-26 11:44:57 -07:00 |
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Alex Forencich
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9834f8365c
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Rework resource management in testbenches, driver, and utils
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-05-01 22:04:43 -07:00 |
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Alex Forencich
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66f5b9fcc1
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Clean up naming in testbenches, driver, and utils
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-04-30 21:48:34 -07:00 |
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Alex Forencich
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bb158d568f
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Add RX indirection table
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-04-10 15:05:32 -07:00 |
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Alex Forencich
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c2fea3a616
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Add port register blocks with support for PHY link status reporting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-04 09:03:37 -07:00 |
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Alex Forencich
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698fd2f104
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Consistent naming of library functions and structs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-24 22:51:37 -07:00 |
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Alex Forencich
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2bd8350276
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Add RX queue mapping module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-23 00:12:22 -07:00 |
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Alex Forencich
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730ccf3a5b
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lib/mqnic: Reorganize library code
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-19 13:13:53 -07:00 |
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