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3,120 Commits 1 Branch 0 Tags
Commit Graph

859 Commits

Author SHA1 Message Date
Alex Forencich
1216f7a76e Offset packet start by 10 bytes to match Linux kernel skb alignment 2020-03-08 21:56:08 -07:00
Alex Forencich
23aef37aff Rewrite resets 2020-03-08 16:56:06 -07:00
Alex Forencich
24eae58e6c merged changes in pcie 2020-03-08 15:25:28 -07:00
Alex Forencich
248a0b4f93 Convert descriptor to DMA operation without storing in table 2020-03-08 00:22:55 -08:00
Alex Forencich
f7a1a7ef95 Add descriptor FIFOs 2020-03-07 22:28:59 -08:00
Alex Forencich
4dd5104f4d Stripe completion queues across event queues 2020-03-06 00:58:30 -08:00
Alex Forencich
627153cd9b Fix signal sizing bug 2020-03-06 00:24:13 -08:00
Alex Forencich
2b14ab2555 Update cmac_pad to pad frames to 60 bytes 2020-02-26 13:36:19 -08:00
Alex Forencich
7ebdceedf2 merged changes in pcie 2020-02-26 13:34:53 -08:00
Alex Forencich
239b7ddd0b Add missing QSFP lpmode connections 2020-02-03 13:52:29 -08:00
Alex Forencich
63fcadaf0f Add missing refclk control connections 2020-01-30 12:22:44 -08:00
Alex Forencich
2f595be70e merged changes in pcie 2020-01-24 13:52:45 -08:00
Alex Forencich
70450a4d89 Add 100G mqnic design for VCU1525 2020-01-16 23:36:32 -08:00
Alex Forencich
26b7b67b9b Add 10G mqnic design for VCU1525 2020-01-16 23:35:00 -08:00
Alex Forencich
e7cadac773 Remove extraneous files 2019-12-31 22:35:25 -08:00
Alex Forencich
81842e3c50 Add 100G mqnic design for Alpha Data board 2019-12-31 21:43:39 -08:00
Alex Forencich
217217b45e Remove unused table fields 2019-12-30 22:02:22 -08:00
Alex Forencich
f642bb7f7e Reserve packet data slot early and release on dequeue fail 2019-12-30 17:49:42 -08:00
Alex Forencich
a501f33c09 Update parameters 2019-12-29 16:46:25 -08:00
Alex Forencich
0955a4101f Fix signal widths 2019-12-29 16:45:32 -08:00
Alex Forencich
3690fdeb7d Pull out pipeline parameters 2019-12-28 01:16:16 -08:00
Alex Forencich
58200e9851 Fix testbench 2019-12-28 01:15:40 -08:00
Alex Forencich
db9e1df1fa Update pipelining to enable URAM inference 2019-12-28 01:13:57 -08:00
Alex Forencich
f97ff4407b Change driver model max packet size 2019-12-23 14:41:52 -08:00
Alex Forencich
cbde1abaf9 Add CMAC pad module 2019-12-23 14:40:51 -08:00
Alex Forencich
96bb5feead merged changes in pcie 2019-12-23 14:39:18 -08:00
Alex Forencich
45a33b8293 Fix scheduler bug 2019-12-16 14:13:01 -08:00
Alex Forencich
7a68abbb84 Split control and data descriptor paths to DMA engine 2019-12-13 14:15:25 -08:00
Alex Forencich
88e31d0ccb Connect PCIe credit interface to DMA cores 2019-12-13 12:41:50 -08:00
Alex Forencich
59d39ca7ec merged changes in pcie 2019-12-07 18:53:55 -08:00
Alex Forencich
4dafedca27 Reschedule queue if necessary 2019-12-06 14:21:20 -08:00
Alex Forencich
6270278c75 Add RSS support 2019-12-06 14:15:16 -08:00
Alex Forencich
b5d7bd15b4 Add rx_hash module and testbenches 2019-12-05 13:47:07 -08:00
Alex Forencich
0e7a91d927 Connect RQ sequence number 2019-12-03 18:19:17 -08:00
Alex Forencich
936cfd9524 merged changes in pcie 2019-12-03 15:48:38 -08:00
Alex Forencich
317aa34db5 Expose control bits 2019-11-21 15:12:49 -08:00
Alex Forencich
463f2053b0 Add port register port_mtu 2019-11-18 16:30:32 -08:00
Alex Forencich
03465b4b25 Fix parameter 2019-11-18 16:27:02 -08:00
Alex Forencich
489506e4c0 Add FPGA ID register 2019-11-17 12:46:27 -08:00
Alex Forencich
445f80e6f2 Connect QSPI flash on Alpha Data board 2019-11-17 01:01:52 -08:00
Alex Forencich
33be402b16 Update widths 2019-11-14 00:02:10 -08:00
Alex Forencich
bce2756c0c Parametrize checksum offload 2019-11-13 23:49:50 -08:00
Alex Forencich
f36773660d Set flash ID 2019-11-06 15:05:32 -08:00
Alex Forencich
c954b55da9 Remove tx_scheduler_tdma_rr module 2019-11-05 22:10:47 -08:00
Alex Forencich
3655a6df00 Use new TDMA scheduler control module 2019-11-05 22:09:51 -08:00
Alex Forencich
93de8a1b32 Remove extraneous init code 2019-11-05 18:32:36 -08:00
Alex Forencich
e43c011e33 Update testbenches 2019-11-05 18:31:41 -08:00
Alex Forencich
7fb022abe1 Add tx_scheduler_ctrl_tdma module 2019-11-05 18:24:22 -08:00
Alex Forencich
f53a6b20e8 Add timeslot count to port registers 2019-11-05 16:59:40 -08:00
Alex Forencich
f65b139797 Add scheduler control input to tx_scheduler_rr 2019-11-05 16:56:10 -08:00