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Author SHA1 Message Date
Alex Forencich
6e974aca27 Driver update for Linux kernel API change 2020-03-26 16:12:56 -07:00
Alex Forencich
566dfa07e7 Read DMA timing optimizations 2020-03-26 14:34:48 -07:00
Alex Forencich
08d92fd138 Add pipeline stage for memory write generation to improve completion handling throughput 2020-03-24 21:58:48 -07:00
Alex Forencich
f8ce39c585 Timing optimization 2020-03-24 19:41:02 -07:00
Alex Forencich
060320010d Don't configure MSI if already configured 2020-03-02 21:16:09 -08:00
Alex Forencich
37934485af Timing optimization for ram_wrap computation 2020-02-28 13:22:35 -08:00
Alex Forencich
983610d6d9 Timing optimization for mask computation 2020-02-28 13:02:26 -08:00
Alex Forencich
50124ce66d Timing optimization 2020-02-28 01:01:37 -08:00
Alex Forencich
db4d0a8f94 Timing optimizations 2020-02-27 20:00:37 -08:00
Alex Forencich
092c72ba66 Compute req_last_tlp in advance 2020-02-27 18:19:45 -08:00
Alex Forencich
18bf537f4f Fix register size 2020-02-27 15:47:18 -08:00
Alex Forencich
a00589e5a3 Timing optimizations 2020-02-27 15:24:24 -08:00
Alex Forencich
bd0482fc96 Update script for sysfs changes 2020-02-26 12:21:36 -08:00
Alex Forencich
8d087ecc92 Consolidate example driver code 2020-02-13 13:16:05 -08:00
Alex Forencich
ec2ceb8e56 Timing optimizations 2020-01-24 13:51:30 -08:00
Alex Forencich
3bad28d626 Add VCU1525 AXI example design 2020-01-15 22:43:33 -08:00
Alex Forencich
e14f6c6f0e Remove unused signals 2019-12-13 15:33:12 -08:00
Alex Forencich
dfd9744b3e PCIe DMA write bandwidth optimizations 2019-12-13 15:31:37 -08:00
Alex Forencich
a6d64bbcbb Remove extraneous character 2019-12-07 14:36:32 -08:00
Alex Forencich
d561195dc8 Add get_data_credits to TLP 2019-12-07 00:54:16 -08:00
Alex Forencich
7567db1818 Add credit-based flow control to DMA cores 2019-12-06 23:24:36 -08:00
Alex Forencich
00858212c6 Placeholder values for flow control credit outputs 2019-12-06 19:16:05 -08:00
Alex Forencich
60a2813fbc Fix indentation 2019-12-05 22:09:04 -08:00
Alex Forencich
f3a6cec13a Use nonblocking assign 2019-12-03 15:47:58 -08:00
Alex Forencich
8985c6dbf3 Add RQ sequence number inputs, operation table, TX_LIMIT parameter to ultrascale write DMA modules 2019-12-03 15:46:36 -08:00
Alex Forencich
a1d0fb810f Reorganize 2019-12-02 15:27:27 -08:00
Alex Forencich
2afef8c6d8 Fix use before define 2019-12-02 15:18:08 -08:00
Alex Forencich
80dafd5870 Check FIFO depth 2019-12-02 15:15:24 -08:00
Alex Forencich
2dbe6e19ab Reset mask FIFO pointers 2019-12-02 14:07:17 -08:00
Alex Forencich
a7be8e8f87 Clear the sequence number valid bits 2019-11-27 16:43:15 -08:00
Alex Forencich
546ef162dd Rewrite reset 2019-11-26 16:44:46 -08:00
Alex Forencich
4c8fcef230 Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules 2019-11-26 16:30:30 -08:00
Alex Forencich
c5a0d05b47 Add OP_TABLE_SIZE parameter to testbenches 2019-11-26 00:00:49 -08:00
Alex Forencich
e7bd0a62f1 Implement RQ sequence numbers in Ultrascale models 2019-11-25 18:07:49 -08:00
Alex Forencich
bbcdcc17bc Rename OP_TAG_WIDTH to OP_TABLE_SIZE 2019-11-25 14:59:53 -08:00
Alex Forencich
176e1159a3 Update python parameter computation to match verilog clog2 2019-11-24 00:01:33 -08:00
Alex Forencich
f6f8e556ef Update tag parameters 2019-11-23 21:18:46 -08:00
Alex Forencich
6c6e3c8212 Remove extraneous parameter connections 2019-11-23 21:15:33 -08:00
Alex Forencich
b2c5004962 Fix discontinue masks 2019-11-23 00:20:21 -08:00
Alex Forencich
a77effe885 Remove quotes 2019-11-17 12:51:13 -08:00
Alex Forencich
ee532a2472 Check tag count based on target device 2019-11-15 14:57:23 -08:00
Alex Forencich
52c502227f Remove unused client tag ports and parameters 2019-11-15 00:55:13 -08:00
Alex Forencich
34c97150e8 Fix get_free_tag 2019-11-04 14:11:24 -08:00
Alex Forencich
097244162e Add VCU108 example design 2019-11-01 18:19:23 -07:00
Alex Forencich
4fcea4e875 Add ExaNIC X25 example design 2019-10-30 17:13:25 -07:00
Alex Forencich
c9193109d1 Rename example designs 2019-10-30 16:48:58 -07:00
Alex Forencich
c43a3eb41a Fix latch inference 2019-10-22 16:03:58 -07:00
Alex Forencich
458a7fc598 Prioritize read request passthrough 2019-10-20 23:30:16 -07:00
Alex Forencich
771c3af93f Remove debug code 2019-10-20 23:21:21 -07:00
Alex Forencich
f2694d8ba3 Update readme 2019-10-17 19:50:49 -07:00