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Author SHA1 Message Date
Alex Forencich
c6f342ef01 Respect enable signal 2018-11-28 01:18:48 -08:00
Alex Forencich
89c52d4eec Fix bit width warning 2018-11-26 23:27:06 -08:00
Alex Forencich
061756f667 Add AXI stream mux module 2018-11-26 23:25:46 -08:00
Alex Forencich
28fa143ae5 Add Ultrascale PCIe DMA modules and testbenches 2018-11-26 23:23:54 -08:00
Alex Forencich
008a7167c7 Add AXI_MAX_BURST_SIZE parameter to PCIe AXI master 2018-11-26 18:03:54 -08:00
Alex Forencich
d81ee9487a Add some more comments 2018-11-26 15:56:13 -08:00
Alex Forencich
24f709573c Only store on valid transfer in 2018-11-26 13:18:38 -08:00
Alex Forencich
1dcc091201 Adjustments for 64 bit datapath 2018-11-26 13:17:41 -08:00
Alex Forencich
8c7eb13c0d Properly handle truncated packet 2018-11-26 13:12:50 -08:00
Alex Forencich
a6809a6b57 Use constants instead of magic numbers 2018-11-26 13:07:50 -08:00
Alex Forencich
c3d4aeda48 Use logical operators 2018-11-08 23:36:05 -08:00
Alex Forencich
038688a223 Add priority encoder and arbiter modules 2018-10-29 17:55:47 -07:00
Alex Forencich
6e46c8e32d Add PCIe tag manager 2018-10-29 17:54:10 -07:00
Alex Forencich
ff617532e0 Add Ultrascale PCIe RC demux 2018-10-29 17:03:19 -07:00
Alex Forencich
31e43ff7c1 Add enable and drop ports to CQ demux 2018-10-29 16:28:26 -07:00
Alex Forencich
e0b2416100 Add AXI model 2018-10-23 22:39:12 -07:00
Alex Forencich
4c9c493aa4 Add Ultrascale PCIe AXI master module and testbenches 2018-10-23 22:28:06 -07:00
Alex Forencich
d34a3e881e Add Ultrascale PCIe AXI master write module and testbenches 2018-10-23 22:26:04 -07:00
Alex Forencich
5a02ba2cb1 Use yield from more consistently 2018-10-23 21:24:39 -07:00
Alex Forencich
3250740f96 Add Ultrascle PCIe MSI shim 2018-10-23 21:12:05 -07:00
Alex Forencich
8b3c9ca794 Add pulse merge module 2018-10-23 21:11:31 -07:00
Alex Forencich
7d5eaae4c8 Add Ultrascle PCIe CQ demux 2018-10-23 21:10:01 -07:00
Alex Forencich
b3ebb04491 Add Ultrascale PCIe AXI master read module and testbenches 2018-10-23 20:50:48 -07:00
Alex Forencich
ab82ea5296 Match IP core ordering 2018-10-16 18:02:28 -07:00
Alex Forencich
6f9c2a1ed2 Add MSI support to Ultrascale PCIe model 2018-10-15 14:18:27 -07:00
Alex Forencich
35ccc2ffd5 Add pause signals 2018-10-15 14:17:00 -07:00
Alex Forencich
4adaa480ca Mask out old field value 2018-10-15 13:52:05 -07:00
Alex Forencich
22850707a6 Address is relative to beginning of region 2018-10-15 13:51:43 -07:00
Alex Forencich
be8ef351ce Fix off-by-one error 2018-10-15 13:51:19 -07:00
Alex Forencich
8ada97200f Update signal widths 2018-10-15 13:41:29 -07:00
Alex Forencich
325df5152f Don't reimplement mem_write for MSI and MSI-X 2018-10-15 11:39:33 -07:00
Alex Forencich
15fdbfeba7 Add attr and tc parameters to mem_read and mem_write 2018-10-15 11:35:37 -07:00
Alex Forencich
e19c84c092 Add msi_register_signal 2018-10-15 10:37:35 -07:00
Alex Forencich
bafae02651 Add MSI test 2018-10-15 00:10:39 -07:00
Alex Forencich
997db1e141 Implment MSI support in RootComplex 2018-10-15 00:08:22 -07:00
Alex Forencich
80c8e01bfd Add issue_msi_interrupt and issue_msix_interrupt 2018-10-15 00:07:40 -07:00
Alex Forencich
45f3614afb Add MSI_CAP_LEN and MSIX_CAP_LEN 2018-10-15 00:06:57 -07:00
Alex Forencich
76dccafe0e Consolidate MSI capability objects 2018-10-15 00:05:37 -07:00
Alex Forencich
2b9e4ccb78 Add get_capability_offset to TreeItem 2018-10-15 00:00:13 -07:00
Alex Forencich
cbd1577129 yield config_read and config_write 2018-10-14 23:59:03 -07:00
Alex Forencich
9f4e62333a Rename parameter to dev 2018-10-14 23:57:53 -07:00
Alex Forencich
6a02c753e9 Incrementally build tree 2018-10-14 23:43:04 -07:00
Alex Forencich
a4e2a65902 Memory writes don't get assigned tags 2018-10-14 20:30:44 -07:00
Alex Forencich
0e601554cb Set address in set_be and set_be_data 2018-10-14 20:29:34 -07:00
Alex Forencich
c047716ae8 The only locked completions are for locked memory reads 2018-10-06 17:28:21 -07:00
Alex Forencich
2059e3b16f Generate is_eof_0 2018-10-06 17:27:16 -07:00
Alex Forencich
a2a43dd11d Fix parity polarity 2018-10-06 17:00:51 -07:00
Alex Forencich
0928bf80bb Fix sign error 2018-10-02 00:26:37 -07:00
Alex Forencich
c4da967da9 Correct lower address 2018-10-01 18:08:56 -07:00
Alex Forencich
51019f0d62 Fix read TLP handling 2018-10-01 17:47:05 -07:00