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2,751 Commits 1 Branch 0 Tags
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702 Commits

Author SHA1 Message Date
Alex Forencich
ae5a029720 Update PCIe model configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-21 18:49:17 -07:00
Alex Forencich
03a49d7bc6 Add 25G mqnic design for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-19 23:43:22 -07:00
Alex Forencich
218f2e2bb3 25G designs use double width sync datapath by default 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 23:31:36 -07:00
Alex Forencich
4b6a96d5ee Add mqnic core logic for Intel P-Tile 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 23:15:54 -07:00
Alex Forencich
b50c389b4a merged changes in pcie 2022-07-18 23:08:51 -07:00
Alex Forencich
c76e152804 Rename cmac_ts_insert to mac_ts_insert 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:27:27 -07:00
Alex Forencich
e47175e5f2 Add 100G mqnic design for BittWare 250-SoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:26:22 -07:00
Alex Forencich
7235484825 Add 25G mqnic design for BittWare 250-SoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:26:12 -07:00
Alex Forencich
ef5b2449dc Add stretched PTP PPS output 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:58 -07:00
Alex Forencich
676f3edd2d Add TX PTP clock to port map module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:39 -07:00
Alex Forencich
b1240bdcae Remove extraneous wires 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:10 -07:00
Alex Forencich
2baae23f94 Minor cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:24:55 -07:00
Alex Forencich
e0d92172d3 Separate PTP TX clock input 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:24:41 -07:00
Alex Forencich
969169c315 Clean up module instantiation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 16:19:30 -07:00
Alex Forencich
f29f72bab9 Change interval 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 01:18:55 -07:00
Alex Forencich
f19d993d8b Rework build_images settings 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 01:18:42 -07:00
Alex Forencich
6b0df7f33f Rework RX request generation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-09 14:43:39 -07:00
Alex Forencich
33b798540e Change hex format in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-09 14:20:48 -07:00
Alex Forencich
729c3a0458 Update for PCIe shim changes, enable TLP straddling on US/US+ devices, and use 256 tags on US+ devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-08 22:07:18 -07:00
Alex Forencich
3c1865a81e merged changes in pcie 2022-07-06 23:19:43 -07:00
Alex Forencich
c95e8f70f2 Update PCIe TLP interface parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 14:31:10 -07:00
Alex Forencich
5595953d5a merged changes in pcie 2022-06-05 14:30:42 -07:00
Alex Forencich
a5d7833bd9 Update testbenches for new version of cocotbext-pcie 2022-06-05 00:24:42 -07:00
Alex Forencich
21b0f014a5 Switch to MSI-X 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:58:29 -07:00
Alex Forencich
6cda5f857c merged changes in pcie 2022-06-02 23:36:46 -07:00
Alex Forencich
dd2853bf40 Update testbenches for latest version of cocotbext-pcie 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-30 13:10:39 -07:00
Alex Forencich
ae55dcc432 Add missing parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-30 13:09:34 -07:00
Alex Forencich
5da044826d Add board-level configuration parameter for TDMA BER module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-18 11:25:58 -07:00
Alex Forencich
0c7bdb5635 Add missing QSFP28 control signal connections on AU200 and AU250 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-18 01:30:19 -07:00
Alex Forencich
ed2d34153d Use PHY rx_status signal for link status detection 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-17 00:46:05 -07:00
Alex Forencich
5058b797d2 merged changes in eth 2022-05-16 23:23:27 -07:00
Alex Forencich
2b33698f9b Fix alignment 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 13:25:13 -07:00
Alex Forencich
814a51a37c Use 128 KB RX RAM size for 25G designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 13:24:56 -07:00
Alex Forencich
827cb1ea1d Pipeline arbitration delay in muxes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:35:39 -07:00
Alex Forencich
01aa6a885b Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:32:28 -07:00
Alex Forencich
a020225304 Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:30:14 -07:00
Alex Forencich
42cf40f338 merged changes in pcie 2022-05-15 19:27:48 -07:00
Alex Forencich
48e525f62a merged changes in eth 2022-05-15 19:00:00 -07:00
Alex Forencich
9653caf09b Add 25G mqnic design for Cisco Nexus K3P-Q 2022-05-09 14:02:13 -07:00
Alex Forencich
ba9ef590b7 Use Cisco Nexus part numbers for Cisco Nexus boards 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-09 13:43:47 -07:00
Alex Forencich
835f0d38f0 Update PTP subsystem to use separate clock for improved stability 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-06 17:46:16 -07:00
Alex Forencich
6656a14528 merged changes in eth 2022-05-06 00:22:55 -07:00
Alex Forencich
18d5c325bf Fix CMAC RX PTP timestamps 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-05 23:21:11 -07:00
Alex Forencich
c2fea3a616 Add port register blocks with support for PHY link status reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-04 09:03:37 -07:00
Alex Forencich
f67c704b11 Update placement constraints for hierarchy changes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-02 13:16:20 -07:00
Alex Forencich
cfdd6f5455 Decouple transmit completion handling from PTP timestamping 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-01 17:41:47 -07:00
Alex Forencich
53f3547ef5 Rework hierarchy to move port-specific logic out of mqnic_core and into mqnic_interface and new port-level modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-29 14:32:57 -07:00
Alex Forencich
2d5e82f42a apps: Fix application module symbol search path to include core mqnic module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-25 00:48:56 -07:00
Alex Forencich
d5c2566dff Add statistics collection for AXI DMA IF 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-23 13:12:50 -07:00
Alex Forencich
2bd8350276 Add RX queue mapping module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-23 00:12:22 -07:00