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Author SHA1 Message Date
Alex Forencich
190d75df9d Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream FIFO 2017-11-20 20:10:41 -08:00
Alex Forencich
a5524287ca Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream register 2017-11-20 20:09:48 -08:00
Alex Forencich
a0b21db746 Improve checks in axis_ep 2017-11-20 15:43:54 -08:00
Alex Forencich
c9cc9006a3 Add last_cycle_user parameter to axis_ep 2017-11-20 15:43:32 -08:00
Alex Forencich
cb2221b39b Use correct path 2017-11-12 18:36:15 -08:00
Alex Forencich
a51109c7c4 Use latest python 2017-11-12 18:30:08 -08:00
Alex Forencich
a35d1a8e7c Fix CI 2017-11-12 18:22:41 -08:00
Alex Forencich
7dc58e5d49 Add tid signal to axis_ep 2017-11-12 18:17:33 -08:00
Alex Forencich
cf6a01fffe Add ML605 SGMII design 2017-07-22 11:07:23 -07:00
Alex Forencich
eb47bea9a1 Use correct clock in testbench 2017-06-09 21:28:08 -07:00
Alex Forencich
77211926f2 Fix classifier logic 2017-06-09 21:27:29 -07:00
Alex Forencich
9a507b388d Update LFSR module 2017-06-09 21:17:28 -07:00
Alex Forencich
69253d2d83 Update VCU108 example design 2017-06-01 06:48:50 -07:00
Alex Forencich
1b6816b06f Add ML605 RGMII example design 2017-05-31 20:24:43 -07:00
Alex Forencich
de00b3e233 Rename ML605 example design 2017-05-31 20:06:32 -07:00
Alex Forencich
e376c805d2 Update ML605 reference design 2017-05-31 19:52:43 -07:00
Alex Forencich
9fdc36450a Update NexysVideo reference design 2017-05-31 19:44:39 -07:00
Alex Forencich
a8a423da0e Update Atlys example design 2017-05-31 19:35:40 -07:00
Alex Forencich
a3b5d5d167 Update RGMII PHY interface and add RGMII MAC wrappers 2017-05-31 18:40:49 -07:00
Alex Forencich
bb9e789645 Update GMII PHY interface and add GMII MAC wrappers 2017-05-31 18:40:18 -07:00
Alex Forencich
8ff4312601 Update MAC modules to use new modules 2017-05-31 18:37:33 -07:00
Alex Forencich
817e7c2667 Add AXI stream GMII RX and TX modules and testbenches 2017-05-31 16:11:20 -07:00
Alex Forencich
b0a4448e69 Add clk_enable and mii_select inputs to GMII and RGMII endpoints 2017-05-31 16:08:05 -07:00
Alex Forencich
0fc986041e Fix example design LED logic 2017-05-19 17:44:29 -07:00
Alex Forencich
57a16b7d54 Add ML605 example design 2017-05-19 17:33:07 -07:00
Alex Forencich
db3bbfdf20 merged changes in axis 2017-05-18 13:52:23 -07:00
Alex Forencich
3e2b94f6c7 Return False instead of None for mismatched objects 2017-05-18 13:52:05 -07:00
Alex Forencich
2e3b15239b Update Vivado IP 2017-05-18 13:49:10 -07:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
6c37731841 merged changes in axis 2017-05-18 13:36:02 -07:00
Alex Forencich
3b0cfbbfed Use extend instead of for loop 2017-05-18 13:35:42 -07:00
Alex Forencich
aebe0549dd Happy new year 2017-05-18 13:35:11 -07:00
Alex Forencich
c2e459c971 Connect transceiver control lines 2017-03-09 17:14:14 -08:00
Alex Forencich
3b47b422fa Fix Vivado clock groups 2016-10-06 17:52:23 -07:00
Alex Forencich
77ecbd7dcb Makefile updates 2016-10-05 17:41:00 -07:00
Alex Forencich
d5928ee776 Trim UDP and IP payloads to proper length 2016-10-05 17:33:05 -07:00
Alex Forencich
270641b7a3 Update UDP modules and example designs to utilize UDP checksum modules 2016-09-30 22:15:21 -07:00
Alex Forencich
4e522e52af Clean up endpoint modules 2016-09-30 22:02:29 -07:00
Alex Forencich
0b6614e8d4 Add UDP checksum generator modules and testbenches 2016-09-30 21:59:04 -07:00
Alex Forencich
15330486e8 Convert GMII and RGMII shims to use generic IO components 2016-09-29 20:10:10 -07:00
Alex Forencich
d13abd76c4 Add generic IO components 2016-09-29 20:07:29 -07:00
Alex Forencich
88150c9d5f Update and rework endpoints, update testbenches 2016-09-13 15:24:02 -07:00
Alex Forencich
64354e0b60 merged changes in axis 2016-09-12 14:08:45 -07:00
Alex Forencich
5fa36eeaa7 Rework endpoints, update testbenches 2016-09-12 13:38:34 -07:00
Alex Forencich
0691c9d61b Fix output pipeline issue 2016-09-02 10:43:21 -07:00
Alex Forencich
306c0ea590 Rework mux logic 2016-08-29 19:25:43 -07:00
Alex Forencich
86ffbd98e8 merged changes in axis 2016-08-28 14:13:55 -07:00
Alex Forencich
4245e2bf00 Rework mux logic 2016-08-24 16:53:13 -07:00
Alex Forencich
3207a2b7d2 Remove redundant code 2016-08-23 09:25:19 -07:00
Alex Forencich
bd0d05411b merged changes in axis 2016-08-22 08:56:24 -07:00