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6 Commits

Author SHA1 Message Date
Alex Forencich
72a35c08ef Clean up FMC+ pins on HTG-9200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:55:19 -07:00
Alex Forencich
bdc974a60c Reorganize HTG-9200 PLL config 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:34:11 -07:00
Alex Forencich
efb3747967 Add IO delay false paths to HTG-9200 constraints file 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-20 21:15:20 -07:00
Alex Forencich
4a65e3594c Connect all PLL control lines on HTG-9200 board 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-20 01:17:49 -07:00
Alex Forencich
50b6f53387 Update testbench clock frequencies 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-15 01:53:31 -07:00
Alex Forencich
d3fb11b2c3 Use unified 10G/25G design for HTG9200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 21:35:42 -07:00