84 Commits

Author	SHA1	Message	Date
Alex Forencich	f082196b4a	Expose EVENT_QUEUE_INDEX_WIDTH parameter at top-level	2022-03-29 23:15:06 -07:00
Alex Forencich	cbd9d0dfc6	Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports	2022-03-28 17:23:27 -07:00
Alex Forencich	09128df360	Add SCHED_PER_IF parameter to split scheduler count from port count	2022-03-28 15:20:33 -07:00
Alex Forencich	dfae34ed25	Pass through PTP pipelining settings	2022-03-28 00:50:29 -07:00
Alex Forencich	fdabde6d0f	Remove deprecated assignments	2022-03-15 17:52:12 -07:00
Alex Forencich	1291d7b1b7	Add pipeline registers to TDMA BER modules	2022-03-15 17:40:27 -07:00
Alex Forencich	2909d205de	Remove unused files	2022-02-16 17:40:28 -08:00
Alex Forencich	3997e0d95b	Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter	2022-02-15 18:01:43 -08:00
Alex Forencich	627ac359d5	Add layer 2 ingress/egress modules	2022-02-13 23:09:41 -08:00
Alex Forencich	e86d47f667	Improve parameter handling in start_xmit	2022-01-27 23:42:32 -08:00
Alex Forencich	155aa5caae	Block in start_xmit when ring is full	2022-01-27 23:34:38 -08:00
Alex Forencich	f98d831014	Ensure that info ring location is empty when sending packets	2022-01-27 23:21:32 -08:00
Alex Forencich	2132a8d98f	Fix index handling in driver model	2022-01-26 09:30:41 -08:00
Alex Forencich	137a6778da	Combine interface control blocks	2022-01-15 21:53:13 -08:00
Alex Forencich	335a5e890b	Initial implementation of shared interface datapath	2021-12-31 14:33:31 -08:00
Alex Forencich	ce21774f06	Register space reorganization	2021-12-29 22:31:46 -08:00
Alex Forencich	7a43618e3c	Use start_soon instead of fork	2021-12-10 20:43:21 -08:00
Alex Forencich	7e3d8606fc	Rework window creation	2021-12-02 16:46:56 -08:00
Alex Forencich	ebd80e7267	Test multiple ports	2021-11-30 14:12:34 -08:00
Alex Forencich	9d817af8d1	Test all interfaces	2021-11-30 00:57:41 -08:00
Alex Forencich	639117e53f	Adjust clock connections to improve connection to testbench	2021-11-30 00:16:47 -08:00
Alex Forencich	8f887005e5	Update Ethernet interface configuration detection in testbenches	2021-11-22 17:04:50 -08:00
Alex Forencich	74f4c6fc2d	Support using separate clock for PTP timestamps on RX path	2021-11-18 23:56:51 -08:00
Alex Forencich	c2d2b441fb	Add missing symlink	2021-11-17 18:29:26 -08:00
Alex Forencich	605965fec9	Add mqnic core logic module for AXI	2021-11-17 18:16:40 -08:00
Alex Forencich	5bf9de656c	Update testbenches	2021-11-17 18:08:40 -08:00
Alex Forencich	bd8a0513ed	Add mqnic core logic for Stratix 10 GX/SX/TX/MX	2021-11-07 13:28:12 -08:00
Alex Forencich	620791e562	Add TDMA testbench	2021-09-13 17:11:39 -07:00
Alex Forencich	d24c53a2ad	Add application section	2021-09-09 16:01:26 -07:00
Alex Forencich	97e3daa36c	Extract information from design instead of env vars	2021-09-08 16:44:58 -07:00
Alex Forencich	c920272e84	Use interface address widths directly instead of BAR size parameters	2021-09-08 14:51:18 -07:00
Alex Forencich	cef144e376	Expose DMA_LEN_WIDTH and DMA_TAG_WIDTH parameters	2021-09-08 00:18:11 -07:00
Alex Forencich	8cf16c182b	More descriptive parameter names (SYNC instead of INT)	2021-09-07 01:29:35 -07:00
Alex Forencich	15dec9458a	Add statistics counter subsystem	2021-09-05 23:03:22 -07:00
Alex Forencich	9ccd43d470	Add statistics collection modules	2021-09-05 18:28:37 -07:00
Alex Forencich	ef00d5ccfd	Add parameters for FIFO output pipeline register depth	2021-09-02 14:45:18 -07:00
Alex Forencich	f3eeb653d1	Fix test	2021-09-02 00:00:37 -07:00
Alex Forencich	37a558e4f6	Add pipeline FIFOs	2021-08-31 22:30:45 -07:00
Alex Forencich	915a915d6e	Enable PCIe flow control in core tests	2021-08-31 20:38:08 -07:00
Alex Forencich	bdbdc11841	Initial commit of core logic	2021-08-31 18:42:19 -07:00
Alex Forencich	c926fd2ca1	Remove extraneous imports	2021-06-28 22:35:22 -07:00
minseongg	9af504a6c0	Update cmac_pad testbench	2021-06-28 22:33:57 -07:00
minseongg	8db2faddc6	Update cmac_pad testbench	2021-06-28 22:33:57 -07:00
minseongg	dc5c8232f9	Add cmac_pad testbench	2021-06-28 22:33:57 -07:00
Alex Forencich	32abea89fa	Update testbenches	2021-03-06 20:30:25 -08:00
Alex Forencich	c0c2f933c0	Rework sim_build output directory, fix default makefile target	2020-12-29 17:28:53 -08:00
Alex Forencich	0c0fdc479b	Update testbenches for async send/recv	2020-12-18 17:40:36 -08:00
Alex Forencich	b5ee772761	Migrate test infrastructure to cocotb	2020-12-15 16:52:20 -08:00
Alex Forencich	a37d9b3465	New transceiver control reigster definitions	2020-09-19 17:25:58 -07:00
Alex Forencich	3284ec3848	New I2C register definitions	2020-09-19 17:25:58 -07:00