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7 Commits

Author SHA1 Message Date
Alex Forencich
70dc92c24e Rework TLP interface parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 13:27:04 -07:00
Alex Forencich
d2c72d3583 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 22:28:05 -07:00
Alex Forencich
90959b8795 Add default_nettype none and resetall directives 2021-10-20 17:49:30 -07:00
Alex Forencich
b2e34cd12a Byte count only needs 3 bits for single DWORD operations 2021-10-03 11:53:24 -07:00
Alex Forencich
ebac1a8be6 Derive length from op_read 2021-10-03 11:51:22 -07:00
Alex Forencich
04a80a4d35 Rework FIFO implementation for pcie_axil_master_minimal 2021-10-03 11:48:47 -07:00
Alex Forencich
2984b5b09d Copy pcie_axil_master as pcie_axil_master_minimal 2021-09-30 22:38:28 -07:00