FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity
419 Commits 1 Branch 0 Tags
Commit Graph

419 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Alex Forencich
74e4322d43 Fix bug in example design core logic 2022-01-17 21:45:49 -08:00
Alex Forencich
625f3c9823 Lock package versions 2021-12-27 16:54:25 -08:00
Alex Forencich
7ab512bd32 Specify min tox and venv versions 2021-12-27 16:53:42 -08:00
Alex Forencich
4ce150e588 Use available python 3 2021-12-27 13:52:23 -08:00
Alex Forencich
25f6dcb383 Fix alignment 2021-12-16 00:30:07 -08:00
Andreas Braun
01b97322c1 Fix reg to wire declaration 
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
 2021-12-16 00:27:43 -08:00
Alex Forencich
bac4e4066f Use start_soon instead of fork 2021-12-10 17:44:37 -08:00
Ulrich Langenbach
5e708ca4c7 Fix multi-driven net issue when S_RAM_SEL_WIDTH = 0 
the same as fixed in verilog-pcie 3a124837115e51e2273ab7d1c61d80ee01f891c1
in dma_ram_demux_rd.v adapted to module dma_ram_demux_wr.v
 2021-12-10 17:39:49 +01:00
Alex Forencich
17d7353523 Indexing updates 2021-12-02 16:59:16 -08:00
Alex Forencich
3a12483711 Fix multi-driven net issue when S_RAM_SEL_WIDTH = 0 2021-12-02 16:50:26 -08:00
Alex Forencich
a2e2919add Update readme 2021-11-18 16:34:43 -08:00
Alex Forencich
d1210d02a3 Add example design for ZCU106 2021-11-18 16:33:39 -08:00
Alex Forencich
0830ca6a7a Add example design for VCU1525 2021-11-18 16:32:38 -08:00
Alex Forencich
fb4b32fba0 Add example design for VCU118 2021-11-18 16:31:55 -08:00
Alex Forencich
cef69d1e1f Add example design for VCU108 2021-11-18 16:31:18 -08:00
Alex Forencich
6740ddafaf Add example design for ExaNIC X25 2021-11-18 16:29:52 -08:00
Alex Forencich
0cbe4897da Add example design for Alveo U50 2021-11-18 16:28:39 -08:00
Alex Forencich
068ea6edc2 Add example design for Alveo U280 2021-11-18 16:27:48 -08:00
Alex Forencich
12fea955d2 Add example design for Alveo U250 2021-11-18 16:26:43 -08:00
Alex Forencich
6e5f9f33f2 Add example design for Alveo U200 2021-11-18 16:25:59 -08:00
Alex Forencich
057edebc36 Add example design for ADM-PCIE-9V3 2021-11-18 16:21:28 -08:00
Alex Forencich
9632a40ad7 Parameter cleanup 2021-11-18 14:23:47 -08:00
Alex Forencich
667076ee39 Testbench cleanup 2021-11-18 13:50:32 -08:00
Alex Forencich
a330c6e7f0 Testbench cleanup 2021-11-18 13:45:55 -08:00
Alex Forencich
419ee057c8 Fix instance name 2021-11-18 13:44:46 -08:00
Alex Forencich
6920845989 Update example design testbenches 2021-11-17 17:21:57 -08:00
Alex Forencich
2c3a5f4bda Update testbenches 2021-11-17 17:21:35 -08:00
Alex Forencich
63e7df0044 Fix makefile 2021-11-17 16:43:27 -08:00
Alex Forencich
78badc447f Update pcie_if model 2021-11-17 01:00:24 -08:00
Alex Forencich
e898f7bdc2 Accept any completion status-related DMA error 2021-11-16 00:54:52 -08:00
Alex Forencich
0d1af9ba55 Use correct completer IDs 2021-11-16 00:44:36 -08:00
Alex Forencich
6cafb46c49 Include TLP in log messages 2021-11-16 00:33:44 -08:00
Alex Forencich
b3145508ed Remove debug code 2021-11-16 00:10:50 -08:00
Alex Forencich
b64269c2e7 Fix widths 2021-11-16 00:10:10 -08:00
Alex Forencich
7c511ef1a9 Clean up signal names 2021-11-16 00:09:55 -08:00
Alex Forencich
5b528158df Remove deprecated assignments 2021-11-09 11:55:12 -08:00
Alex Forencich
8a7f410aaf Don't read address/data if valid is not set 2021-11-07 19:03:10 -08:00
Alex Forencich
9883e776c3 Parameter cleanup 2021-11-03 20:46:40 -07:00
Alex Forencich
e31345071d Add AXI RAM for example designs 2021-11-03 19:12:55 -07:00
Alex Forencich
c54dba8a94 Update readme 2021-11-03 18:38:33 -07:00
Alex Forencich
f4ffdb727d Add example design for BittWare 520N-MX 2021-11-03 18:13:40 -07:00
Alex Forencich
f2fad37273 Add example design for Stratix 10 MX development kit 2021-11-03 18:12:17 -07:00
Alex Forencich
9297c518f1 Add example design for ExaNIC X10 2021-11-03 18:10:17 -07:00
Alex Forencich
d43067a805 Add example design for fb2CG@KU15P 2021-11-03 18:09:46 -07:00
Alex Forencich
84009500a8 Add example design core logic modules 2021-11-03 01:51:10 -07:00
Alex Forencich
5c5876ff1d Add PCIe interface shim for Stratix 10 GX/SX/TX/MX H-Tile/L-Tile 2021-11-02 22:29:57 -07:00
Alex Forencich
d2c72d3583 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 22:28:05 -07:00
Alex Forencich
fab74d1d0f Update test durations 2021-11-02 18:29:35 -07:00
Alex Forencich
47a2570647 Set class code to memory controller, set subsystem ID based on board 2021-11-02 14:39:33 -07:00
Alex Forencich
ad157ca3ad Enable interrupts 2021-11-02 14:35:42 -07:00