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Author SHA1 Message Date
Alex Forencich
74f4c6fc2d Support using separate clock for PTP timestamps on RX path 2021-11-18 23:56:51 -08:00
Alex Forencich
af3b6312a9 Add PTP_USE_SAMPLE_CLOCK parameter to testbenches 2021-11-18 21:12:06 -08:00
Alex Forencich
fca6341636 Add flash size check for Alveo boards 2021-11-18 16:23:37 -08:00
Alex Forencich
c2d2b441fb Add missing symlink 2021-11-17 18:29:26 -08:00
Alex Forencich
605965fec9 Add mqnic core logic module for AXI 2021-11-17 18:16:40 -08:00
Alex Forencich
5bf9de656c Update testbenches 2021-11-17 18:08:40 -08:00
Alex Forencich
dc75f86980 merged changes in pcie 2021-11-17 17:38:57 -08:00
Alex Forencich
6920845989 Update example design testbenches 2021-11-17 17:21:57 -08:00
Alex Forencich
2c3a5f4bda Update testbenches 2021-11-17 17:21:35 -08:00
Alex Forencich
63e7df0044 Fix makefile 2021-11-17 16:43:27 -08:00
Alex Forencich
78badc447f Update pcie_if model 2021-11-17 01:00:24 -08:00
Alex Forencich
e898f7bdc2 Accept any completion status-related DMA error 2021-11-16 00:54:52 -08:00
Alex Forencich
0d1af9ba55 Use correct completer IDs 2021-11-16 00:44:36 -08:00
Alex Forencich
6cafb46c49 Include TLP in log messages 2021-11-16 00:33:44 -08:00
Alex Forencich
b3145508ed Remove debug code 2021-11-16 00:10:50 -08:00
Alex Forencich
b64269c2e7 Fix widths 2021-11-16 00:10:10 -08:00
Alex Forencich
7c511ef1a9 Clean up signal names 2021-11-16 00:09:55 -08:00
Alex Forencich
5b528158df Remove deprecated assignments 2021-11-09 11:55:12 -08:00
Alex Forencich
8a7f410aaf Don't read address/data if valid is not set 2021-11-07 19:03:10 -08:00
Alex Forencich
76e18d2af8 Add 10G mqnic design for Stratix 10 MX dev kit 2021-11-07 13:59:05 -08:00
Alex Forencich
bd8a0513ed Add mqnic core logic for Stratix 10 GX/SX/TX/MX 2021-11-07 13:28:12 -08:00
Alex Forencich
dfdf880c3a Add Stratix 10 JTAG IDs 2021-11-06 16:20:54 -07:00
Alex Forencich
7ab18f8602 Increase event FIFO depth 2021-11-06 16:14:49 -07:00
Alex Forencich
fb0f6f67f7 Remove debug code 2021-11-06 16:14:32 -07:00
Alex Forencich
f8a24d1c46 Add attributes to RAMs for proper synthesis in Quartus 2021-11-06 16:14:22 -07:00
Alex Forencich
cefb4568e7 merged changes in axi 2021-11-06 15:22:50 -07:00
Alex Forencich
b4bdfb6542 Add FIFO output register in AXI lite crossbar modules 2021-11-06 15:20:19 -07:00
Alex Forencich
0b16849b57 Add attributes to RAMs for proper synthesis in Quartus 2021-11-04 20:43:13 -07:00
Alex Forencich
aa89471cca Add bus_num port to mqnic_core_pcie 2021-11-03 21:40:19 -07:00
Alex Forencich
e0cfb0c107 merged changes in pcie 2021-11-03 20:47:25 -07:00
Alex Forencich
ce6717cbee merged changes in eth 2021-11-03 20:47:21 -07:00
Alex Forencich
9883e776c3 Parameter cleanup 2021-11-03 20:46:40 -07:00
Alex Forencich
e31345071d Add AXI RAM for example designs 2021-11-03 19:12:55 -07:00
Alex Forencich
c54dba8a94 Update readme 2021-11-03 18:38:33 -07:00
Alex Forencich
f4ffdb727d Add example design for BittWare 520N-MX 2021-11-03 18:13:40 -07:00
Alex Forencich
f2fad37273 Add example design for Stratix 10 MX development kit 2021-11-03 18:12:17 -07:00
Alex Forencich
9297c518f1 Add example design for ExaNIC X10 2021-11-03 18:10:17 -07:00
Alex Forencich
d43067a805 Add example design for fb2CG@KU15P 2021-11-03 18:09:46 -07:00
Alex Forencich
84009500a8 Add example design core logic modules 2021-11-03 01:51:10 -07:00
Alex Forencich
4cda6b07dd Update readme 2021-11-03 00:48:59 -07:00
Alex Forencich
d052264659 Add 520N-MX 10G example design 2021-11-03 00:48:06 -07:00
Alex Forencich
9e44987f60 Reorganize PHY instances 2021-11-02 23:30:48 -07:00
Alex Forencich
728e86c554 Update QSF/SDC files 2021-11-02 23:30:06 -07:00
Alex Forencich
5c5876ff1d Add PCIe interface shim for Stratix 10 GX/SX/TX/MX H-Tile/L-Tile 2021-11-02 22:29:57 -07:00
Alex Forencich
d2c72d3583 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 22:28:05 -07:00
Alex Forencich
74f32c6a59 Add missing PHY instance ports 2021-11-02 20:28:26 -07:00
Alex Forencich
0aee872452 merged changes in axis 2021-11-02 20:23:33 -07:00
Alex Forencich
96a26e7a54 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 20:22:47 -07:00
Alex Forencich
fab74d1d0f Update test durations 2021-11-02 18:29:35 -07:00
Alex Forencich
38c85a6bcd Set subsystem ID based on board, remove unnecessary configuration settings 2021-11-02 15:32:55 -07:00