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571 Commits 1 Branch 0 Tags
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277 Commits

Author SHA1 Message Date
Alex Forencich
0a53e7c990 Improve completion credit count tracking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-22 16:45:00 -07:00
Alex Forencich
23595150dd Fix TLP mux pause 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-21 02:30:38 -07:00
Alex Forencich
3d2feb36dc Add completion buffer management logic to DMA interface modu 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-30 18:37:44 -07:00
Alex Forencich
b2de81fbd9 Add RCB status output to shims 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-30 14:26:32 -07:00
Alex Forencich
f59c5b78c8 Minor refactor of PCIe read request TLP size computation signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-28 01:02:24 -07:00
Alex Forencich
8ad370ac99 Properly handle PCIE_TAG_COUNT setting of 32 or less 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-17 19:12:09 -07:00
Alex Forencich
2f449d0b29 Rework write done handling in DMA ram demux module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-15 16:44:40 -07:00
Alex Forencich
4c82a8f465 Improve status FIFO utilization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-15 01:52:13 -07:00
Alex Forencich
2d307a6d60 Add busy status outputs to DMA interface modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-12 16:05:44 -07:00
Alex Forencich
1a4692bf17 Increase flow control credit threshold for controlling the transmission of posted and non-posted requests in UltraScale shim 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-10 14:51:36 -07:00
Alex Forencich
6591849fe8 Generate wr_done output based only on wr_cmd_valid, not wr_cmd_be 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-10 14:46:47 -07:00
Alex Forencich
6bfaef78bd Properly handle 4KB read requests in UltraScale shim 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 21:52:27 -07:00
Alex Forencich
633037d032 Fix direction of config signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 21:40:08 -07:00
Alex Forencich
5e396ceb87 Rename seg_rc_hdr to seg_rq_hdr 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 21:19:48 -07:00
Alex Forencich
916faa0bdd Add IRQ rate limit module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 12:02:26 -07:00
Alex Forencich
d038ba9853 Minor cleanup of MSI-X module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-03 17:19:21 -07:00
Alex Forencich
a1e53e5e46 Fix latch inference 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-03 01:20:39 -07:00
Alex Forencich
a2f07db39f Remove redundant abort signal connection 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-14 14:55:01 -07:00
Alex Forencich
60dd672f6d Move pause signal connection to improve timing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-14 14:54:27 -07:00
Alex Forencich
edf9b260ab Rename module to match file name 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-14 14:53:15 -07:00
Alex Forencich
d6d59a5675 Don't force DMA RAM into MLABs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-05 16:25:18 -07:00
Alex Forencich
91450fcab7 PCIe flow control is handled in shim; remove flow control from PCIe DMA interface 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 13:47:02 -07:00
Alex Forencich
3f3be1e14d Implement flow control for P-Tile 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-02 22:57:27 -07:00
Alex Forencich
7f0bd00170 Implement flow control for Stratix 10 shim 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-01 13:19:01 -07:00
Alex Forencich
9c434687a8 Add flow control credit counter to TLP FIFO MUX module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-31 17:35:07 -07:00
Alex Forencich
ad5a322ee1 Add PCIe flow control credit count module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-31 17:24:43 -07:00
Alex Forencich
1dfdd8b0e3 Timing optimization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-31 17:24:03 -07:00
Alex Forencich
b1b82a3f2b Add pause inputs to TLP mux modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-29 17:16:05 -07:00
Alex Forencich
0d9b1d0fb0 Implement flow control in UltraScale shim 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-26 14:01:00 -07:00
Alex Forencich
be6bb907c9 Register MSI-X control signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 00:32:19 -07:00
Alex Forencich
2a727e04f7 Add PCIe interface shim for Intel Stratix 10 DX/Agilex P-Tile 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-12 23:53:34 -07:00
Alex Forencich
743f3817ce Fix alignment 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-11 23:36:53 -07:00
Alex Forencich
e15fe3cbc9 Fix port widths 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-11 23:32:19 -07:00
Alex Forencich
edd1d546d5 Fix 256-bit RC interface framing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-06 23:14:19 -07:00
Alex Forencich
19b1af0388 Update Xilinx UltraScale shims to support TLP straddling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-04 00:46:07 -07:00
Alex Forencich
103d7abdd9 Rework framing signal generation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-03 22:38:16 -07:00
Alex Forencich
a44f9852c2 Update Stratix 10 H-tile/L-tile shim to support segments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:48:46 -07:00
Alex Forencich
24dd0af398 Adjust MSI-X TLP port configuration for single segment, single DWORD operations 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:41:51 -07:00
Alex Forencich
5658af86e0 Add PCIe TLP FIFO mux module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:41:27 -07:00
Alex Forencich
cc1278f9d9 Update PCIe TLP mux to handle multiple segments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:40:35 -07:00
Alex Forencich
23705eb873 Update PCIe TLP demux to handle segments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:39:38 -07:00
Alex Forencich
fc42368bd5 Add segmented PCIe TLP FIFO module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 15:35:57 -07:00
Alex Forencich
a5e81d7575 Ensure wide RAMs are marked for MLAB inference 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 15:28:44 -07:00
Alex Forencich
b044ac10ff Optimize offset_next computation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 15:25:45 -07:00
Alex Forencich
93c2804b1b Add pipeline register after barrel shift 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 15:24:28 -07:00
Alex Forencich
8797aa481f Rework status FIFOs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 15:24:05 -07:00
Alex Forencich
2d48255ba3 Add mux and demux wrapper generators 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-13 01:06:01 -07:00
Alex Forencich
056500dbf4 Avoid zero-width replication 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-13 00:52:29 -07:00
Alex Forencich
72e8bad417 Normalize interfaces 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-13 00:51:37 -07:00
Alex Forencich
4818f2595c Fix initial reg value 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-13 00:27:44 -07:00