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7 Commits

Author SHA1 Message Date
Alex Forencich
2d307a6d60 Add busy status outputs to DMA interface modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-12 16:05:44 -07:00
Alex Forencich
a5dcb3d27c Add support for writing immediate data to DMA IF modules 2022-04-04 12:40:42 -07:00
Alex Forencich
4bbd187567 Add statistics outputs to AXI DMA IF modules 2022-03-31 17:56:05 -07:00
Alex Forencich
c62df81292 Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH 2022-02-15 00:39:46 -08:00
Alex Forencich
d9c4b173e9 Update parameters 2022-02-01 00:23:52 -08:00
Alex Forencich
90959b8795 Add default_nettype none and resetall directives 2021-10-20 17:49:30 -07:00
Alex Forencich
e0167eedd8 Add AXI DMA interface modules and testbenches 2021-10-20 13:04:17 -07:00