Alex Forencich
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23595150dd
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Fix TLP mux pause
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-06-21 02:30:38 -07:00 |
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Alex Forencich
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a2f07db39f
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Remove redundant abort signal connection
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-14 14:55:01 -07:00 |
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Alex Forencich
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60dd672f6d
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Move pause signal connection to improve timing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-14 14:54:27 -07:00 |
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Alex Forencich
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9c434687a8
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Add flow control credit counter to TLP FIFO MUX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-31 17:35:07 -07:00 |
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Alex Forencich
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1dfdd8b0e3
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Timing optimization
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-31 17:24:03 -07:00 |
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Alex Forencich
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b1b82a3f2b
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Add pause inputs to TLP mux modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-29 17:16:05 -07:00 |
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Alex Forencich
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5658af86e0
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Add PCIe TLP FIFO mux module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-02 23:41:27 -07:00 |
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