FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity
571 Commits 1 Branch 0 Tags
Commit Graph

277 Commits

Author SHA1 Message Date
Alex Forencich
fbec32e4f2 Use whole status FIFO memory 2018-12-06 17:36:12 -08:00
Alex Forencich
5db9cddf6e Reorganize and simplify burst length computation code 2018-11-29 15:20:01 -08:00
Alex Forencich
8ab02e4220 Remove some debug code 2018-11-28 11:14:26 -08:00
Alex Forencich
89c8e87f95 Add status FIFO to manage write responses 2018-11-28 11:13:53 -08:00
Alex Forencich
c6f342ef01 Respect enable signal 2018-11-28 01:18:48 -08:00
Alex Forencich
89c52d4eec Fix bit width warning 2018-11-26 23:27:06 -08:00
Alex Forencich
061756f667 Add AXI stream mux module 2018-11-26 23:25:46 -08:00
Alex Forencich
28fa143ae5 Add Ultrascale PCIe DMA modules and testbenches 2018-11-26 23:23:54 -08:00
Alex Forencich
008a7167c7 Add AXI_MAX_BURST_SIZE parameter to PCIe AXI master 2018-11-26 18:03:54 -08:00
Alex Forencich
d81ee9487a Add some more comments 2018-11-26 15:56:13 -08:00
Alex Forencich
24f709573c Only store on valid transfer in 2018-11-26 13:18:38 -08:00
Alex Forencich
1dcc091201 Adjustments for 64 bit datapath 2018-11-26 13:17:41 -08:00
Alex Forencich
8c7eb13c0d Properly handle truncated packet 2018-11-26 13:12:50 -08:00
Alex Forencich
a6809a6b57 Use constants instead of magic numbers 2018-11-26 13:07:50 -08:00
Alex Forencich
c3d4aeda48 Use logical operators 2018-11-08 23:36:05 -08:00
Alex Forencich
038688a223 Add priority encoder and arbiter modules 2018-10-29 17:55:47 -07:00
Alex Forencich
6e46c8e32d Add PCIe tag manager 2018-10-29 17:54:10 -07:00
Alex Forencich
ff617532e0 Add Ultrascale PCIe RC demux 2018-10-29 17:03:19 -07:00
Alex Forencich
31e43ff7c1 Add enable and drop ports to CQ demux 2018-10-29 16:28:26 -07:00
Alex Forencich
4c9c493aa4 Add Ultrascale PCIe AXI master module and testbenches 2018-10-23 22:28:06 -07:00
Alex Forencich
d34a3e881e Add Ultrascale PCIe AXI master write module and testbenches 2018-10-23 22:26:04 -07:00
Alex Forencich
3250740f96 Add Ultrascle PCIe MSI shim 2018-10-23 21:12:05 -07:00
Alex Forencich
8b3c9ca794 Add pulse merge module 2018-10-23 21:11:31 -07:00
Alex Forencich
7d5eaae4c8 Add Ultrascle PCIe CQ demux 2018-10-23 21:10:01 -07:00
Alex Forencich
b3ebb04491 Add Ultrascale PCIe AXI master read module and testbenches 2018-10-23 20:50:48 -07:00
Alex Forencich
b5cfb9d025 Handshaking fixes 2018-09-26 20:11:25 -07:00
Alex Forencich
c25a13041e Add Ultascale PCIe AXI lite master module and testbenches 2018-09-25 21:09:20 -07:00