Alex Forencich
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60dd672f6d
|
Move pause signal connection to improve timing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-14 14:54:27 -07:00 |
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Alex Forencich
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edf9b260ab
|
Rename module to match file name
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-14 14:53:15 -07:00 |
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Alex Forencich
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d6d59a5675
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Don't force DMA RAM into MLABs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-05 16:25:18 -07:00 |
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Alex Forencich
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91450fcab7
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PCIe flow control is handled in shim; remove flow control from PCIe DMA interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-03 13:47:02 -07:00 |
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Alex Forencich
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3f3be1e14d
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Implement flow control for P-Tile
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-02 22:57:27 -07:00 |
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Alex Forencich
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53ee26f3ec
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Use latest version of cocotbext-pcie
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-08-01 13:25:51 -07:00 |
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Alex Forencich
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7f0bd00170
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Implement flow control for Stratix 10 shim
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-01 13:19:01 -07:00 |
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Alex Forencich
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9c434687a8
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Add flow control credit counter to TLP FIFO MUX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-31 17:35:07 -07:00 |
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Alex Forencich
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ad5a322ee1
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Add PCIe flow control credit count module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-31 17:24:43 -07:00 |
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Alex Forencich
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1dfdd8b0e3
|
Timing optimization
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-31 17:24:03 -07:00 |
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Alex Forencich
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b1b82a3f2b
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Add pause inputs to TLP mux modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-29 17:16:05 -07:00 |
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Alex Forencich
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0d9b1d0fb0
|
Implement flow control in UltraScale shim
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-26 14:01:00 -07:00 |
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Alex Forencich
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a5fe40cd42
|
Fix JTAG index
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-22 22:34:26 -07:00 |
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Alex Forencich
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a53509de68
|
Add instance names
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-22 22:34:04 -07:00 |
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Alex Forencich
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90c65dfed7
|
Fix PBA offsets
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-22 22:33:38 -07:00 |
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Alex Forencich
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5fe904545c
|
Testbench cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-13 16:35:51 -07:00 |
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Alex Forencich
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fc90d7f44d
|
Strip version number
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-13 00:40:43 -07:00 |
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Alex Forencich
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05f51ed05c
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-13 00:32:33 -07:00 |
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Alex Forencich
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be6bb907c9
|
Register MSI-X control signals
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-13 00:32:19 -07:00 |
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Alex Forencich
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dbcd211ce1
|
Add example design for DE10-Agilex
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-13 00:31:59 -07:00 |
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Alex Forencich
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c5382f5e7f
|
Add example design for Stratix 10 DX dev kit
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-13 00:31:39 -07:00 |
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Alex Forencich
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cf3029364d
|
Add P-Tile example design core module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-13 00:31:13 -07:00 |
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Alex Forencich
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2a727e04f7
|
Add PCIe interface shim for Intel Stratix 10 DX/Agilex P-Tile
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-12 23:53:34 -07:00 |
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Alex Forencich
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3f334dbbbb
|
Use MSI-X in example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-12 23:32:51 -07:00 |
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Alex Forencich
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e2588cd995
|
Clean up TCL scripts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-12 16:23:54 -07:00 |
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Alex Forencich
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743f3817ce
|
Fix alignment
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-11 23:36:53 -07:00 |
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Alex Forencich
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e15fe3cbc9
|
Fix port widths
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-11 23:32:19 -07:00 |
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Alex Forencich
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edd1d546d5
|
Fix 256-bit RC interface framing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-06 23:14:19 -07:00 |
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Alex Forencich
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ce233c6c2b
|
Use latest version of cocotbext-pcie
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-04 13:17:55 -07:00 |
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Alex Forencich
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a17c33e3c6
|
Update example designs to enable TLP straddling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-04 01:31:15 -07:00 |
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Alex Forencich
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19b1af0388
|
Update Xilinx UltraScale shims to support TLP straddling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-04 00:46:07 -07:00 |
|
Alex Forencich
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103d7abdd9
|
Rework framing signal generation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-03 22:38:16 -07:00 |
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Alex Forencich
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a44f9852c2
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Update Stratix 10 H-tile/L-tile shim to support segments
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-02 23:48:46 -07:00 |
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Alex Forencich
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26c7128b7e
|
Tie off unused port
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-02 23:42:03 -07:00 |
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Alex Forencich
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24dd0af398
|
Adjust MSI-X TLP port configuration for single segment, single DWORD operations
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-02 23:41:51 -07:00 |
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Alex Forencich
|
5658af86e0
|
Add PCIe TLP FIFO mux module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-02 23:41:27 -07:00 |
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Alex Forencich
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cc1278f9d9
|
Update PCIe TLP mux to handle multiple segments
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-02 23:40:35 -07:00 |
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Alex Forencich
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23705eb873
|
Update PCIe TLP demux to handle segments
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-02 23:39:38 -07:00 |
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Alex Forencich
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fc42368bd5
|
Add segmented PCIe TLP FIFO module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-02 15:35:57 -07:00 |
|
Alex Forencich
|
a5e81d7575
|
Ensure wide RAMs are marked for MLAB inference
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-02 15:28:44 -07:00 |
|
Alex Forencich
|
b044ac10ff
|
Optimize offset_next computation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-02 15:25:45 -07:00 |
|
Alex Forencich
|
93c2804b1b
|
Add pipeline register after barrel shift
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-02 15:24:28 -07:00 |
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Alex Forencich
|
8797aa481f
|
Rework status FIFOs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-02 15:24:05 -07:00 |
|
Alex Forencich
|
87e155949c
|
Add a simple block transfer measurement
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-06-19 22:52:16 -07:00 |
|
Alex Forencich
|
9b74e02408
|
Add jinja2 to tox.ini
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-06-13 01:36:12 -07:00 |
|
Alex Forencich
|
1ca13c3af2
|
Add TLP mux and demux tests
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-06-13 01:06:29 -07:00 |
|
Alex Forencich
|
2d48255ba3
|
Add mux and demux wrapper generators
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-06-13 01:06:01 -07:00 |
|
Alex Forencich
|
056500dbf4
|
Avoid zero-width replication
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-06-13 00:52:29 -07:00 |
|
Alex Forencich
|
72e8bad417
|
Normalize interfaces
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-06-13 00:51:37 -07:00 |
|
Alex Forencich
|
4818f2595c
|
Fix initial reg value
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-06-13 00:27:44 -07:00 |
|