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Author SHA1 Message Date
Alex Forencich
7775e7774d merged changes in axis 2018-07-02 16:26:21 -07:00
Alex Forencich
ffc63e4b0d Update readme 2018-07-02 16:25:29 -07:00
Alex Forencich
3063bba54b Update testbenches to use wait 2018-07-02 16:19:35 -07:00
Alex Forencich
9390c3639b More endpoint updates 2018-07-02 14:13:47 -07:00
Alex Forencich
63f9bbeced Update endpoints 2018-07-02 13:20:49 -07:00
Alex Forencich
4cb51ac84e merged changes in axis 2018-07-02 10:25:51 -07:00
Alex Forencich
268d011b89 Add wait method to sink 2018-06-30 00:21:26 -07:00
Alex Forencich
2ebffeb223 Be more pythonic 2018-06-30 00:21:02 -07:00
Alex Forencich
8982b4f4e1 Fix modsell pin 2018-06-29 13:00:41 -07:00
Alex Forencich
cd51821bf7 Add parameters 2018-06-22 18:56:05 -07:00
Alex Forencich
5b7646ccda Rework ARP subsystem 2018-06-18 13:59:58 -07:00
Alex Forencich
25d1b373cc Use don't care bits 2018-06-14 15:20:20 -07:00
Alex Forencich
6368529b6f Add clock frequency annotation 2018-06-14 13:42:10 -07:00
Alex Forencich
e4672915e6 Update testbenches to use instances() 2018-06-13 22:43:11 -07:00
Alex Forencich
20486d438a merged changes in axis 2018-06-13 22:36:26 -07:00
Alex Forencich
c5837daa2f Update testbenches to use instances() 2018-06-13 22:26:10 -07:00
Alex Forencich
298ae4defa Update MAC module instantiation 2018-06-13 22:16:02 -07:00
Alex Forencich
8e1f14e9a7 Add VCU118 10G example design 2018-06-13 19:30:07 -07:00
Alex Forencich
05c6743473 Update xdc 2018-06-13 19:18:59 -07:00
Alex Forencich
f4d7edf23f Add VCU118 example design 2018-06-13 14:33:07 -07:00
Alex Forencich
415f723edc Fix clock name 2018-06-11 16:37:34 -07:00
Alex Forencich
fea477db09 Add unused ports 2018-06-11 16:36:44 -07:00
Alex Forencich
3ae97c71a0 Add documentation 2018-06-04 18:21:55 -07:00
Alex Forencich
e95b39b36d Update iddr/oddr Altera device support 2018-06-04 18:20:31 -07:00
Alex Forencich
c31757552b Add crosspoint design 2018-05-31 16:27:56 -07:00
Alex Forencich
855b593ce5 Minor updates to 10G example designs 2018-05-31 16:05:41 -07:00
Alex Forencich
3e28af152a Fix CI 2018-02-27 11:00:31 -08:00
Alex Forencich
6727e5a0bd Happy new year 2018-02-27 01:47:56 -08:00
Alex Forencich
d0ef5f94a4 merge changes in axis 2018-02-27 01:46:35 -08:00
Alex Forencich
7c6da337b0 Happy new year 2018-02-27 01:39:25 -08:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
0807a54c32 merged changes in axis 2018-02-26 12:45:29 -08:00
Alex Forencich
5df7efe516 Happy new year 2018-02-26 12:25:20 -08:00
Alex Forencich
3063a761e5 Support both versions of ML605 2018-02-26 00:18:14 -08:00
Alex Forencich
bd27156f35 AXI stream updates 2018-02-26 00:08:08 -08:00
Alex Forencich
18787c2eed merged changes in axis 2017-12-01 00:02:34 -08:00
Alex Forencich
c33985d7ba Remove extraneous parameter 2017-11-21 08:54:21 -08:00
Alex Forencich
93688dc88e Update readme 2017-11-21 00:21:15 -08:00
Alex Forencich
4ec4c901e8 Whitespace fixes 2017-11-21 00:18:09 -08:00
Alex Forencich
b00eaf4d3c Add tkeep signal and update testbench for stat counter 2017-11-21 00:17:42 -08:00
Alex Forencich
ad0e3e1eb5 Whitespace fixes and testbench update for frame joiner 2017-11-21 00:16:15 -08:00
Alex Forencich
a1a6d523e3 Update FIFO instances and testbenches for COBS encoder and decoder 2017-11-21 00:14:26 -08:00
Alex Forencich
0edafd58ac Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream tap 2017-11-20 23:45:34 -08:00
Alex Forencich
4ef4ef2622 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL register 2017-11-20 21:34:25 -08:00
Alex Forencich
b0d7820f5b Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL FIFO 2017-11-20 21:32:46 -08:00
Alex Forencich
d16f19f67e Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream rate limiter 2017-11-20 21:31:41 -08:00
Alex Forencich
772e433ee9 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame length adjuster 2017-11-20 21:30:26 -08:00
Alex Forencich
de590517a9 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream switch 2017-11-20 20:17:20 -08:00
Alex Forencich
91a7169f46 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream crosspoint 2017-11-20 20:16:21 -08:00
Alex Forencich
496c63bd1c Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream arbitrated mux 2017-11-20 20:15:08 -08:00