19 Commits

Author	SHA1	Message	Date
Alex Forencich	2f883681d6	Add pararametrizable output pipeline to FIFOs	2020-09-07 00:14:22 -07:00
Alex Forencich	69de6fd2a4	Convert FIFOs to use DEPTH parameter instead of ADDR_WIDTH	2019-07-18 11:27:25 -07:00
Alex Forencich	3920b2801e	Add short packet tests	2019-03-26 16:39:31 -07:00
Alex Forencich	e0f740457b	Testbench updates	2019-03-07 22:51:40 -08:00
Alex Forencich	f9a5e6803b	Add backpressure tests	2018-12-08 23:59:57 -08:00
Alex Forencich	11d9dbe24a	Merge axis_async_fifo and axis_async_frame_fifo, rename ports	2018-10-25 09:53:38 -07:00
Alex Forencich	3063bba54b	Update testbenches to use wait	2018-07-02 16:19:35 -07:00
Alex Forencich	c5837daa2f	Update testbenches to use instances()	2018-06-13 22:26:10 -07:00
Alex Forencich	5df7efe516	Happy new year	2018-02-26 12:25:20 -08:00
Alex Forencich	fdb881719c	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async frame FIFO	2017-11-20 20:12:02 -08:00
Alex Forencich	aebe0549dd	Happy new year	2017-05-18 13:35:11 -07:00
Alex Forencich	5fa36eeaa7	Rework endpoints, update testbenches	2016-09-12 13:38:34 -07:00
Alex Forencich	be4034071b	Happy new year	2016-01-05 00:24:20 -08:00
Alex Forencich	364b537312	Synchronize status signals for both clock domains in async frame FIFO	2015-10-09 15:14:54 -07:00
Alex Forencich	30a35c3d73	Convert async fifo to common reset	2015-10-08 12:52:51 -07:00
Alex Forencich	516c50d786	Add FIFO reset tests	2015-07-09 11:13:25 -07:00
Alex Forencich	e65173b7ee	Add overflow, bad_frame, and good_frame status outputs to frame FIFOs	2015-05-12 17:52:41 -07:00
Alex Forencich	02a7f4d5ed	Update testbenches to python 3	2015-03-21 03:32:19 -07:00
Alex Forencich	10e0d7d1bb	Add AXI async frame fifo and testbench	2014-11-08 21:29:39 -08:00