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Author	SHA1	Message	Date
Alex Forencich	4ec4c901e8	Whitespace fixes	2017-11-21 00:18:09 -08:00
Alex Forencich	b00eaf4d3c	Add tkeep signal and update testbench for stat counter	2017-11-21 00:17:42 -08:00
Alex Forencich	ad0e3e1eb5	Whitespace fixes and testbench update for frame joiner	2017-11-21 00:16:15 -08:00
Alex Forencich	a1a6d523e3	Update FIFO instances and testbenches for COBS encoder and decoder	2017-11-21 00:14:26 -08:00
Alex Forencich	0edafd58ac	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream tap	2017-11-20 23:45:34 -08:00
Alex Forencich	4ef4ef2622	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL register	2017-11-20 21:34:25 -08:00
Alex Forencich	b0d7820f5b	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL FIFO	2017-11-20 21:32:46 -08:00
Alex Forencich	d16f19f67e	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream rate limiter	2017-11-20 21:31:41 -08:00
Alex Forencich	772e433ee9	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame length adjuster	2017-11-20 21:30:26 -08:00
Alex Forencich	de590517a9	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream switch	2017-11-20 20:17:20 -08:00
Alex Forencich	91a7169f46	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream crosspoint	2017-11-20 20:16:21 -08:00
Alex Forencich	496c63bd1c	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream arbitrated mux	2017-11-20 20:15:08 -08:00
Alex Forencich	57e700f802	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream demux	2017-11-20 20:14:20 -08:00
Alex Forencich	9e4aa38750	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream mux	2017-11-20 20:13:53 -08:00
Alex Forencich	d50c767482	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream adapter	2017-11-20 20:12:43 -08:00
Alex Forencich	fdb881719c	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async frame FIFO	2017-11-20 20:12:02 -08:00
Alex Forencich	1c7362c717	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame FIFO	2017-11-20 20:11:44 -08:00
Alex Forencich	7d237f55c1	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async FIFO	2017-11-20 20:11:08 -08:00
Alex Forencich	190d75df9d	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream FIFO	2017-11-20 20:10:41 -08:00
Alex Forencich	a5524287ca	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream register	2017-11-20 20:09:48 -08:00
Alex Forencich	a0b21db746	Improve checks in axis_ep	2017-11-20 15:43:54 -08:00
Alex Forencich	c9cc9006a3	Add last_cycle_user parameter to axis_ep	2017-11-20 15:43:32 -08:00
Alex Forencich	cb2221b39b	Use correct path	2017-11-12 18:36:15 -08:00
Alex Forencich	a51109c7c4	Use latest python	2017-11-12 18:30:08 -08:00
Alex Forencich	a35d1a8e7c	Fix CI	2017-11-12 18:22:41 -08:00
Alex Forencich	7dc58e5d49	Add tid signal to axis_ep	2017-11-12 18:17:33 -08:00
Alex Forencich	3e2b94f6c7	Return False instead of None for mismatched objects	2017-05-18 13:52:05 -07:00
Alex Forencich	3b0cfbbfed	Use extend instead of for loop	2017-05-18 13:35:42 -07:00
Alex Forencich	aebe0549dd	Happy new year	2017-05-18 13:35:11 -07:00
Alex Forencich	5fa36eeaa7	Rework endpoints, update testbenches	2016-09-12 13:38:34 -07:00
Alex Forencich	0691c9d61b	Fix output pipeline issue	2016-09-02 10:43:21 -07:00
Alex Forencich	4245e2bf00	Rework mux logic	2016-08-24 16:53:13 -07:00
Alex Forencich	3207a2b7d2	Remove redundant code	2016-08-23 09:25:19 -07:00
Alex Forencich	e989f15ff4	Remove some test cases	2016-08-22 08:17:26 -07:00
Alex Forencich	24f7aee8b2	Add COBS encoder and decoder modules and testbench	2016-08-21 20:03:54 -07:00
Alex Forencich	e6d78b7ca7	Add extra testbench delay	2016-08-04 18:03:24 -07:00
Alex Forencich	a961a9756a	Add FIFO output pipeline registers to aid block RAM output timing closure	2016-08-04 18:03:00 -07:00
Alex Forencich	b44e401b95	Update async FIFO resets	2016-07-27 13:42:44 -07:00
Alex Forencich	c27e74c7d4	Update readme	2016-07-25 13:15:59 -07:00
Alex Forencich	06bfa1944c	Add AXI stream switch module, generator script, and testbench	2016-07-25 13:12:10 -07:00
Alex Forencich	5fe35a79d2	Add tdest support to axis_ep	2016-07-25 11:28:35 -07:00
Alex Forencich	d023213fda	Support generating asymmetric crosspoints	2016-07-24 13:06:59 -07:00
Alex Forencich	52fc34d82e	Assume first tkeep bit is always set	2016-07-20 12:36:59 -07:00
Alex Forencich	6fe4a033e5	Add dedicated pipeline registers for RAM addresses that are not reset	2016-06-27 12:25:18 -07:00
Alex Forencich	385c9cc90a	Fix Vivado block RAM inference	2016-06-27 12:10:36 -07:00
Alex Forencich	4f66059d21	Adjust constant naming	2016-06-27 11:27:04 -07:00
Alex Forencich	f89620008d	Remove reset dependence	2016-06-27 11:26:15 -07:00
Alex Forencich	cab7d367f2	Fix default width	2016-06-27 11:24:36 -07:00
Alex Forencich	be4034071b	Happy new year	2016-01-05 00:24:20 -08:00
Alex Forencich	7a9fdb5fc3	Add default case statements to avoid inferring latches	2015-11-09 14:54:14 -08:00