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332 Commits 1 Branch 0 Tags
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17 Commits

Author SHA1 Message Date
Alex Forencich
073d50d9dc Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8 2022-03-30 16:02:17 -07:00
Alex Forencich
e4b4762474 Handle some zero-valued signal width settings 2021-11-29 00:33:38 -08:00
Alex Forencich
ccbca0c502 Add UPDATE_TID parameter to set MSBs of tid based on source port 2021-11-28 16:25:35 -08:00
Alex Forencich
24863398c5 Decouple tid/tdest signal widths for routing components 2021-11-25 01:18:51 -08:00
Alex Forencich
2972a1fa81 Add default_nettype none and resetall directives 2021-10-20 15:33:38 -07:00
Alex Forencich
4fa3870dea Remove string parameters 2021-06-02 15:08:43 -07:00
Alex Forencich
892ee84bff Delay command until write is acknowledged 2021-05-31 01:32:02 -07:00
Alex Forencich
3579310447 Clear active bit 2021-05-31 01:31:30 -07:00
Alex Forencich
16b174b490 Print addressing configuration 2021-05-30 12:19:01 -07:00
Alex Forencich
e3183862bb tkeep always active inside RAM switch 2021-05-30 12:12:10 -07:00
Alex Forencich
56a3b8fe92 Fix indexed part select error in degenerate case when M_COUNT = 1 2021-05-30 12:11:46 -07:00
Alex Forencich
a7689b6772 Pipeline RAM output in RAM switch 2020-09-03 15:55:45 -07:00
Alex Forencich
4754d94736 Fix backpressure bug 2020-04-17 21:22:07 -07:00
Alex Forencich
f9915b2f31 Refactor 2020-02-19 21:32:00 -08:00
Alex Forencich
406a3d69d1 Rework read handling 2020-02-19 21:24:15 -08:00
Alex Forencich
2876235a72 Throughput optimizations 2020-02-19 18:15:58 -08:00
Alex Forencich
52d1117753 Add AXI stream RAM switch module and testbenches 2020-02-18 01:06:14 -08:00