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1218 Commits

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Author SHA1 Message Date
Alex Forencich
7a68abbb84 Split control and data descriptor paths to DMA engine 2019-12-13 14:15:25 -08:00
Alex Forencich
88e31d0ccb Connect PCIe credit interface to DMA cores 2019-12-13 12:41:50 -08:00
Alex Forencich
59d39ca7ec merged changes in pcie 2019-12-07 18:53:55 -08:00
Alex Forencich
a6d64bbcbb Remove extraneous character 2019-12-07 14:36:32 -08:00
Alex Forencich
d561195dc8 Add get_data_credits to TLP 2019-12-07 00:54:16 -08:00
Alex Forencich
7567db1818 Add credit-based flow control to DMA cores 2019-12-06 23:24:36 -08:00
Alex Forencich
00858212c6 Placeholder values for flow control credit outputs 2019-12-06 19:16:05 -08:00
Alex Forencich
04a3d24ffc Update readme 2019-12-06 14:56:54 -08:00
Alex Forencich
4dafedca27 Reschedule queue if necessary 2019-12-06 14:21:20 -08:00
Alex Forencich
6270278c75 Add RSS support 2019-12-06 14:15:16 -08:00
Alex Forencich
60a2813fbc Fix indentation 2019-12-05 22:09:04 -08:00
Alex Forencich
bcd45fe9f2 Name IRQs 2019-12-05 16:24:46 -08:00
Alex Forencich
b5d7bd15b4 Add rx_hash module and testbenches 2019-12-05 13:47:07 -08:00
Alex Forencich
2fa4f595ee Don't crash with a null device pointer 2019-12-04 13:37:53 -08:00
Alex Forencich
90e2f8f5d0 Check if FPGA needs reset in utilities 2019-12-04 13:37:18 -08:00
Alex Forencich
ef365b9bab Report which ring is full 2019-12-04 13:36:19 -08:00
Alex Forencich
384912e618 Improve sanity checking and error reporting in receive handling 2019-12-04 13:34:56 -08:00
Alex Forencich
c4d17b6a3c Improve sanity checking and error reporting in event queue processing 2019-12-04 13:32:46 -08:00
Alex Forencich
a432a8f472 Dump event queue state 2019-12-04 13:29:40 -08:00
Alex Forencich
0e7a91d927 Connect RQ sequence number 2019-12-03 18:19:17 -08:00
Alex Forencich
936cfd9524 merged changes in pcie 2019-12-03 15:48:38 -08:00
Alex Forencich
f3a6cec13a Use nonblocking assign 2019-12-03 15:47:58 -08:00
Alex Forencich
8985c6dbf3 Add RQ sequence number inputs, operation table, TX_LIMIT parameter to ultrascale write DMA modules 2019-12-03 15:46:36 -08:00
Alex Forencich
a1d0fb810f Reorganize 2019-12-02 15:27:27 -08:00
Alex Forencich
2afef8c6d8 Fix use before define 2019-12-02 15:18:08 -08:00
Alex Forencich
80dafd5870 Check FIFO depth 2019-12-02 15:15:24 -08:00
Alex Forencich
2dbe6e19ab Reset mask FIFO pointers 2019-12-02 14:07:17 -08:00
Alex Forencich
a7be8e8f87 Clear the sequence number valid bits 2019-11-27 16:43:15 -08:00
Alex Forencich
546ef162dd Rewrite reset 2019-11-26 16:44:46 -08:00
Alex Forencich
4c8fcef230 Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules 2019-11-26 16:30:30 -08:00
Alex Forencich
c5a0d05b47 Add OP_TABLE_SIZE parameter to testbenches 2019-11-26 00:00:49 -08:00
Alex Forencich
e7bd0a62f1 Implement RQ sequence numbers in Ultrascale models 2019-11-25 18:07:49 -08:00
Alex Forencich
bbcdcc17bc Rename OP_TAG_WIDTH to OP_TABLE_SIZE 2019-11-25 14:59:53 -08:00
Alex Forencich
176e1159a3 Update python parameter computation to match verilog clog2 2019-11-24 00:01:33 -08:00
Alex Forencich
f6f8e556ef Update tag parameters 2019-11-23 21:18:46 -08:00
Alex Forencich
6c6e3c8212 Remove extraneous parameter connections 2019-11-23 21:15:33 -08:00
Alex Forencich
b2c5004962 Fix discontinue masks 2019-11-23 00:20:21 -08:00
Alex Forencich
f35d576301 Add mqnic-dump utility 2019-11-21 17:08:40 -08:00
Alex Forencich
317aa34db5 Expose control bits 2019-11-21 15:12:49 -08:00
Alex Forencich
e696433ecc Support changing MTU 2019-11-19 13:30:35 -08:00
Alex Forencich
2647f68124 Reset pointers after clearing buffers 2019-11-19 13:12:47 -08:00
Alex Forencich
463f2053b0 Add port register port_mtu 2019-11-18 16:30:32 -08:00
Alex Forencich
03465b4b25 Fix parameter 2019-11-18 16:27:02 -08:00
Alex Forencich
af434c8eba Add state_lock 2019-11-18 16:17:27 -08:00
Alex Forencich
a77effe885 Remove quotes 2019-11-17 12:51:13 -08:00
Alex Forencich
489506e4c0 Add FPGA ID register 2019-11-17 12:46:27 -08:00
Alex Forencich
445f80e6f2 Connect QSPI flash on Alpha Data board 2019-11-17 01:01:52 -08:00
Alex Forencich
ee532a2472 Check tag count based on target device 2019-11-15 14:57:23 -08:00
Alex Forencich
52c502227f Remove unused client tag ports and parameters 2019-11-15 00:55:13 -08:00
Alex Forencich
33be402b16 Update widths 2019-11-14 00:02:10 -08:00