Alex Forencich
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7c6da337b0
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Happy new year
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2018-02-27 01:39:25 -08:00 |
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Alex Forencich
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5df7efe516
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Happy new year
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2018-02-26 12:25:20 -08:00 |
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Alex Forencich
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4ec4c901e8
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Whitespace fixes
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2017-11-21 00:18:09 -08:00 |
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Alex Forencich
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b00eaf4d3c
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Add tkeep signal and update testbench for stat counter
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2017-11-21 00:17:42 -08:00 |
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Alex Forencich
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ad0e3e1eb5
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Whitespace fixes and testbench update for frame joiner
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2017-11-21 00:16:15 -08:00 |
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Alex Forencich
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a1a6d523e3
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Update FIFO instances and testbenches for COBS encoder and decoder
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2017-11-21 00:14:26 -08:00 |
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Alex Forencich
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0edafd58ac
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream tap
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2017-11-20 23:45:34 -08:00 |
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Alex Forencich
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4ef4ef2622
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL register
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2017-11-20 21:34:25 -08:00 |
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Alex Forencich
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b0d7820f5b
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL FIFO
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2017-11-20 21:32:46 -08:00 |
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Alex Forencich
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d16f19f67e
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream rate limiter
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2017-11-20 21:31:41 -08:00 |
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Alex Forencich
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772e433ee9
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame length adjuster
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2017-11-20 21:30:26 -08:00 |
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Alex Forencich
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de590517a9
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream switch
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2017-11-20 20:17:20 -08:00 |
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Alex Forencich
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91a7169f46
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream crosspoint
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2017-11-20 20:16:21 -08:00 |
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Alex Forencich
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496c63bd1c
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream arbitrated mux
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2017-11-20 20:15:08 -08:00 |
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Alex Forencich
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57e700f802
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream demux
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2017-11-20 20:14:20 -08:00 |
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Alex Forencich
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9e4aa38750
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream mux
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2017-11-20 20:13:53 -08:00 |
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Alex Forencich
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d50c767482
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream adapter
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2017-11-20 20:12:43 -08:00 |
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Alex Forencich
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fdb881719c
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async frame FIFO
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2017-11-20 20:12:02 -08:00 |
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Alex Forencich
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1c7362c717
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame FIFO
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2017-11-20 20:11:44 -08:00 |
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Alex Forencich
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7d237f55c1
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async FIFO
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2017-11-20 20:11:08 -08:00 |
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Alex Forencich
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190d75df9d
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream FIFO
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2017-11-20 20:10:41 -08:00 |
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Alex Forencich
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a5524287ca
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream register
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2017-11-20 20:09:48 -08:00 |
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Alex Forencich
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aebe0549dd
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Happy new year
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2017-05-18 13:35:11 -07:00 |
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Alex Forencich
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0691c9d61b
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Fix output pipeline issue
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2016-09-02 10:43:21 -07:00 |
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Alex Forencich
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4245e2bf00
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Rework mux logic
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2016-08-24 16:53:13 -07:00 |
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Alex Forencich
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3207a2b7d2
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Remove redundant code
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2016-08-23 09:25:19 -07:00 |
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Alex Forencich
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24f7aee8b2
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Add COBS encoder and decoder modules and testbench
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2016-08-21 20:03:54 -07:00 |
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Alex Forencich
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a961a9756a
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Add FIFO output pipeline registers to aid block RAM output timing closure
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2016-08-04 18:03:00 -07:00 |
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Alex Forencich
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b44e401b95
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Update async FIFO resets
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2016-07-27 13:42:44 -07:00 |
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Alex Forencich
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06bfa1944c
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Add AXI stream switch module, generator script, and testbench
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2016-07-25 13:12:10 -07:00 |
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Alex Forencich
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d023213fda
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Support generating asymmetric crosspoints
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2016-07-24 13:06:59 -07:00 |
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Alex Forencich
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52fc34d82e
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Assume first tkeep bit is always set
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2016-07-20 12:36:59 -07:00 |
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Alex Forencich
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6fe4a033e5
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Add dedicated pipeline registers for RAM addresses that are not reset
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2016-06-27 12:25:18 -07:00 |
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Alex Forencich
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385c9cc90a
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Fix Vivado block RAM inference
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2016-06-27 12:10:36 -07:00 |
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Alex Forencich
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4f66059d21
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Adjust constant naming
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2016-06-27 11:27:04 -07:00 |
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Alex Forencich
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f89620008d
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Remove reset dependence
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2016-06-27 11:26:15 -07:00 |
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Alex Forencich
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cab7d367f2
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Fix default width
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2016-06-27 11:24:36 -07:00 |
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Alex Forencich
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be4034071b
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Happy new year
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2016-01-05 00:24:20 -08:00 |
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Alex Forencich
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7a9fdb5fc3
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Add default case statements to avoid inferring latches
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2015-11-09 14:54:14 -08:00 |
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Alex Forencich
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0d22a35bd8
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Update output registers, remove extraneous resets, fix constant widths
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2015-11-08 23:05:38 -08:00 |
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Alex Forencich
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0a79f24d3c
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Do not reset datapath registers in crosspoint switch
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2015-11-08 17:27:13 -08:00 |
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Alex Forencich
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5fb4cb159b
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Reorganize register modules
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2015-11-08 16:18:29 -08:00 |
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Alex Forencich
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0f0ebfb87d
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Reorganize FIFO modules
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2015-11-07 01:15:11 -08:00 |
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Alex Forencich
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7ea566e6d2
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Update generate scripts to use argparse
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2015-10-19 19:15:38 -07:00 |
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Alex Forencich
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dcad442e7c
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Improve timing performance of frame length adjust module
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2015-10-19 00:30:50 -07:00 |
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Alex Forencich
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364b537312
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Synchronize status signals for both clock domains in async frame FIFO
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2015-10-09 15:14:54 -07:00 |
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Alex Forencich
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382226ad59
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Don't accept data until reset is complete
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2015-10-08 23:46:59 -07:00 |
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Alex Forencich
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90ac361df5
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Internal synchronous reset on async FIFOs
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2015-10-08 13:03:42 -07:00 |
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Alex Forencich
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30a35c3d73
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Convert async fifo to common reset
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2015-10-08 12:52:51 -07:00 |
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Alex Forencich
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ca11618e6d
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Convert to synchronous resets
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2015-10-08 11:26:32 -07:00 |
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