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429 Commits 1 Branch 0 Tags
Commit Graph

202 Commits

Author SHA1 Message Date
Alex Forencich
7cae50fa10 Support zero-length operations in AXI DMA interface modules 2022-03-30 23:40:02 -07:00
Alex Forencich
3f967c673f Read zero length flag on all paths 2022-03-30 23:39:34 -07:00
Alex Forencich
c62df81292 Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH 2022-02-15 00:39:46 -08:00
Alex Forencich
a65b256b85 Update default SEG_ADDR_WIDTH parameter value for DMA RAM 2022-02-14 22:28:50 -08:00
Alex Forencich
c47332462d Implement USE_AXI_ID for dma_if_axi_rd 2022-02-01 16:29:56 -08:00
Alex Forencich
27f90934fe Refactor to use existing variable 2022-02-01 16:27:13 -08:00
Alex Forencich
a0a7732801 Add missing resets 2022-02-01 16:26:12 -08:00
Alex Forencich
2f6ad1e28d Implement USE_AXI_ID for dma_if_axi_wr 2022-02-01 00:43:21 -08:00
Alex Forencich
d9c4b173e9 Update parameters 2022-02-01 00:23:52 -08:00
Alex Forencich
25f6dcb383 Fix alignment 2021-12-16 00:30:07 -08:00
Andreas Braun
01b97322c1 Fix reg to wire declaration 
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
 2021-12-16 00:27:43 -08:00
Ulrich Langenbach
5e708ca4c7 Fix multi-driven net issue when S_RAM_SEL_WIDTH = 0 
the same as fixed in verilog-pcie 3a124837115e51e2273ab7d1c61d80ee01f891c1
in dma_ram_demux_rd.v adapted to module dma_ram_demux_wr.v
 2021-12-10 17:39:49 +01:00
Alex Forencich
17d7353523 Indexing updates 2021-12-02 16:59:16 -08:00
Alex Forencich
3a12483711 Fix multi-driven net issue when S_RAM_SEL_WIDTH = 0 2021-12-02 16:50:26 -08:00
Alex Forencich
b3145508ed Remove debug code 2021-11-16 00:10:50 -08:00
Alex Forencich
b64269c2e7 Fix widths 2021-11-16 00:10:10 -08:00
Alex Forencich
7c511ef1a9 Clean up signal names 2021-11-16 00:09:55 -08:00
Alex Forencich
5c5876ff1d Add PCIe interface shim for Stratix 10 GX/SX/TX/MX H-Tile/L-Tile 2021-11-02 22:29:57 -07:00
Alex Forencich
d2c72d3583 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 22:28:05 -07:00
Alex Forencich
f612d88288 Rewrite op tag FIFO read in DMA engines 2021-10-31 21:57:26 -07:00
Alex Forencich
90959b8795 Add default_nettype none and resetall directives 2021-10-20 17:49:30 -07:00
Alex Forencich
e0167eedd8 Add AXI DMA interface modules and testbenches 2021-10-20 13:04:17 -07:00
Alex Forencich
c41f0a823a Prevent latch inference 2021-10-03 11:55:27 -07:00
Alex Forencich
b2e34cd12a Byte count only needs 3 bits for single DWORD operations 2021-10-03 11:53:24 -07:00
Alex Forencich
ebac1a8be6 Derive length from op_read 2021-10-03 11:51:22 -07:00
Alex Forencich
04a80a4d35 Rework FIFO implementation for pcie_axil_master_minimal 2021-10-03 11:48:47 -07:00
Alex Forencich
bb74bdf2f7 Update pcie_axil_master module to support arbitrary memory operations 2021-10-03 11:46:55 -07:00
Alex Forencich
eea6b66f3f Add PCIe AXI master modules and testbenches 2021-10-02 00:59:18 -07:00
Alex Forencich
824e9fc758 Resize registers 2021-10-02 00:46:21 -07:00
Alex Forencich
aee1431e74 Remove irrelevant address computation 2021-10-01 15:56:51 -07:00
Alex Forencich
adeb2c6b1c Fix alignment 2021-10-01 13:50:30 -07:00
Alex Forencich
d0705fea9b Minor optimizations to completion TLP size computation logic 2021-10-01 13:00:22 -07:00
Alex Forencich
c044898ec4 One AXI read burst per completion TLP 2021-10-01 00:20:29 -07:00
Alex Forencich
2984b5b09d Copy pcie_axil_master as pcie_axil_master_minimal 2021-09-30 22:38:28 -07:00
Alex Forencich
bc8715decc Hold read completions until pending writes complete 2021-09-25 00:46:55 -07:00
Alex Forencich
b131b2ebbf Rework DMA desc status demux to fix X issue at t=0 2021-09-09 00:58:48 -07:00
Alex Forencich
f566df2c66 Add TLP mux and demux modules 2021-09-08 10:04:38 -07:00
Alex Forencich
1321e8e41a Refactor check 2021-09-05 15:30:37 -07:00
Alex Forencich
8a6abc51ed Add statistics outputs to DMA interface 2021-09-05 15:29:56 -07:00
Alex Forencich
6af4461705 Fix length register widths and max value handling 2021-08-20 16:09:58 -07:00
Alex Forencich
0563eb4727 Check MSBs 2021-08-20 14:12:26 -07:00
Alex Forencich
943731d624 Use new modules in dma_if_mux modules 2021-08-16 18:04:38 -07:00
Alex Forencich
292f73f43d Add DMA RAM demux modules 2021-08-16 18:03:38 -07:00
Alex Forencich
1342e31976 Add DMA IF descriptor mux module 2021-08-16 18:03:22 -07:00
Alex Forencich
ac96ae97d3 Add flow control signals to pcie_us_if 2021-08-11 19:37:51 -07:00
Alex Forencich
811b9daa63 Add missing connection 2021-08-11 19:18:50 -07:00
Alex Forencich
8e19f6edb8 Tie off outputs if configuration read functionality is disabled 2021-08-11 19:17:55 -07:00
Alex Forencich
c47f3f5280 AT is reserved in completions 2021-08-06 01:49:47 -07:00
Alex Forencich
1c424a8a51 Read locked is UR for PCIe endpoints 2021-08-06 01:39:11 -07:00
Alex Forencich
836d14bad6 Add PCIe interface shim for Xilinx UltraScale 2021-08-04 01:03:31 -07:00