155 Commits

Author	SHA1	Message	Date
Alex Forencich	134ce04777	Add configurable serdes pipeline register chain	2019-06-19 00:57:28 -07:00
Alex Forencich	3ba91ce091	Wait for block lock	2019-06-19 00:53:41 -07:00
Alex Forencich	d96a5a449a	Update ARP cache testbench	2019-06-14 00:01:51 -07:00
Alex Forencich	6eff2f0030	Decouple transmit PTP tag enable and transmit PTP timestamp enable	2019-06-09 22:03:24 -07:00
Alex Forencich	82fe5a6bdd	Add PTP timestamp capture logic to MACs	2019-06-07 16:38:36 -07:00
Alex Forencich	659aa67481	Pack start packet strobes into the same signal	2019-06-06 17:13:14 -07:00
Alex Forencich	2efcfdb0a0	Add PTP clock simulation model	2019-06-03 19:08:16 -07:00
Alex Forencich	e181ea5abc	Add PTP clock module and testbench	2019-06-03 19:00:28 -07:00
Alex Forencich	79ec137243	Add PRBS31 generation and checking to 10G PHY	2019-05-10 20:28:45 -07:00
Alex Forencich	e34c72da1f	Add missing parameter	2019-05-10 17:23:55 -07:00
Alex Forencich	b7d297850c	Move 10G PHY interface logic into separate modules	2019-05-10 14:56:18 -07:00
Alex Forencich	696c634726	Add rx_bad_block outputs	2019-04-17 00:16:45 -07:00
Alex Forencich	8e2d936884	Add MII PHY interface, MAC wrappers, and testbenches	2019-03-28 19:18:03 -07:00
Alex Forencich	585ccefa15	Add TX underflow error signal	2019-03-26 12:42:08 -07:00
Alex Forencich	013e88253e	Testbench updates	2019-03-07 23:44:43 -08:00
Alex Forencich	c1fe89db62	Add bit reverse support to serdes endpoint	2019-01-31 18:14:06 -08:00
Alex Forencich	ec38440d89	Add 10G Ethernet MAC/PHY combination modules and testbenches	2019-01-31 18:13:07 -08:00
Alex Forencich	e644ce3895	Add start packet strobe timing outputs to MAC modules	2019-01-31 17:00:23 -08:00
Alex Forencich	a743f6f789	Add zero IFG forced offset start test	2019-01-22 18:47:32 -08:00
Alex Forencich	5b2d4fd465	Add force offset start parameter	2019-01-22 18:46:34 -08:00
Alex Forencich	4d2090a1a5	Fix off-by-one error in control character checks	2019-01-22 14:24:35 -08:00
Alex Forencich	92df3778ea	Fix DIC implementation in testbench	2019-01-22 14:23:29 -08:00
Alex Forencich	dbbbc28059	Add 10G Ethernet PHY modules and testbenches	2019-01-16 18:00:56 -08:00
Alex Forencich	91553e6edf	Add XGMII 10GBASE-R encoder and decoder modules and testbenches	2019-01-16 17:30:07 -08:00
Alex Forencich	c9752f24dd	Add BASE-R SERDES endpoint model	2019-01-16 17:26:19 -08:00
Alex Forencich	5fbd67501c	Clamp ifg_cnt at zero	2019-01-16 17:25:08 -08:00
Alex Forencich	128dc292a1	Add short IFG tests	2019-01-16 13:27:28 -08:00
Alex Forencich	bf94ef56b8	Move ifg parameter	2019-01-16 13:23:02 -08:00
Alex Forencich	fe8a4f9df3	Use constants for control characters	2018-11-11 00:18:32 -08:00
Alex Forencich	6a4b2699ea	End frame reception on any control character	2018-11-11 00:11:27 -08:00
Alex Forencich	25e196e18b	Insert idle characters	2018-11-10 18:56:50 -08:00
Alex Forencich	b195c6450b	Add IFG parameter	2018-11-10 18:23:44 -08:00
Alex Forencich	a49b78b3c3	Add width asserts	2018-11-10 18:23:31 -08:00
Alex Forencich	b6c8cc7125	Append termination control character	2018-11-10 18:16:30 -08:00
Alex Forencich	0159376cda	Simplify IFG count handling	2018-11-10 17:35:31 -08:00
Alex Forencich	d59a0553bd	Change start character handling	2018-11-09 16:51:54 -08:00
Alex Forencich	261ad46a8a	Add enable signals to xgmii model	2018-11-09 16:47:19 -08:00
Alex Forencich	d2fedc4134	Rename ports	2018-11-07 22:35:06 -08:00
Alex Forencich	b3f50ac2c7	Fix comments	2018-11-02 00:40:15 -07:00
Alex Forencich	98fc042489	Convert generated udp_demux to verilog parametrized module	2018-11-02 00:39:52 -07:00
Alex Forencich	81e9aa0c77	Convert generated ip_demux to verilog parametrized module	2018-11-02 00:25:23 -07:00
Alex Forencich	18c4214edb	Convert generated eth_demux to verilog parametrized module	2018-11-02 00:23:31 -07:00
Alex Forencich	470ab887d9	Update mux instances	2018-11-01 00:59:14 -07:00
Alex Forencich	fea1186f57	Convert generated udp_arb_mux to verilog parametrized module	2018-11-01 00:48:26 -07:00
Alex Forencich	554e0a5380	Convert generated ip_arb_mux to verilog parametrized module	2018-11-01 00:40:09 -07:00
Alex Forencich	96cefbe0c1	Convert generated eth_arb_mux to verilog parametrized module	2018-10-31 21:42:28 -07:00
Alex Forencich	67025121ab	Convert generated udp_mux to verilog parametrized module	2018-10-31 18:09:44 -07:00
Alex Forencich	f20312b199	Convert generated ip_mux to verilog parametrized module	2018-10-31 18:08:39 -07:00
Alex Forencich	d28d459d70	Convert generated eth_mux to verilog parametrized module	2018-10-31 15:48:12 -07:00
Alex Forencich	68abccd0a1	Workaround for MyHDL race condition	2018-10-31 13:42:33 -07:00