9 Commits

Author	SHA1	Message	Date
Alex Forencich	6b18e56cb1	Add default_nettype none and resetall directives	2021-10-20 17:29:12 -07:00
Alex Forencich	625c48c59c	Add transceiver reset watchdog	2021-10-17 20:19:04 -07:00
Alex Forencich	247aeae845	Detect bad XGMII encodings in PHY TX	2021-10-16 00:50:48 -07:00
Alex Forencich	9667ef1f9c	Detect sequence errors	2021-10-16 00:03:35 -07:00
Alex Forencich	5e1329a992	Rework PHY bitslip timing	2021-05-05 00:35:43 -07:00
Alex Forencich	134ce04777	Add configurable serdes pipeline register chain	2019-06-19 00:57:28 -07:00
Alex Forencich	79ec137243	Add PRBS31 generation and checking to 10G PHY	2019-05-10 20:28:45 -07:00
Alex Forencich	696c634726	Add rx_bad_block outputs	2019-04-17 00:16:45 -07:00
Alex Forencich	dbbbc28059	Add 10G Ethernet PHY modules and testbenches	2019-01-16 18:00:56 -08:00