Alex Forencich
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7f8bbe30de
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Add application ID
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-21 13:15:45 -07:00 |
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Alex Forencich
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ba70498518
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fpga: Add DMA immediate connections and parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-20 15:00:58 -07:00 |
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Alex Forencich
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eb530475fb
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More expressive flash format register
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-15 18:38:01 -07:00 |
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Alex Forencich
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47f0044099
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fpga/mqnic: Fix incorrect SLR in placement constraints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-14 11:51:10 -07:00 |
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Alex Forencich
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f58d922e8f
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fpga/mqnic: Use correct clock frequencies in 25G testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-13 20:20:01 -07:00 |
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Alex Forencich
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f687aba432
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fpga/mqnic: Update designs to use port mapping modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-13 01:37:10 -07:00 |
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Alex Forencich
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c5d5fe8a64
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fpga/mqnic: Remove unused wires
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-09 23:02:44 -07:00 |
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Alex Forencich
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f082196b4a
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Expose EVENT_QUEUE_INDEX_WIDTH parameter at top-level
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2022-03-29 23:15:06 -07:00 |
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Alex Forencich
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cbd9d0dfc6
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Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports
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2022-03-28 17:23:27 -07:00 |
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Alex Forencich
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09128df360
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Add SCHED_PER_IF parameter to split scheduler count from port count
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2022-03-28 15:20:33 -07:00 |
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Alex Forencich
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dfae34ed25
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Pass through PTP pipelining settings
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2022-03-28 00:50:29 -07:00 |
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Alex Forencich
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e95c132045
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Route PCIe user reset through BUFG
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2022-03-25 01:26:29 -07:00 |
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Alex Forencich
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6f197c7cb4
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Add PHY instances to Ethernet pblocks
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2022-03-24 21:30:55 -07:00 |
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Alex Forencich
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056f78716a
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Add pipeline registers
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2022-03-17 15:39:44 -07:00 |
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Alex Forencich
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0e15a7a16b
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Avoid critical warning from placement constraints when configured with a single interface
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2022-03-17 15:39:13 -07:00 |
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Alex Forencich
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869e7e70d4
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Add Ethernet interface placement constraints for AU250
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2022-03-17 00:51:14 -07:00 |
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Alex Forencich
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25421b8994
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Update placement constraints
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2022-03-15 15:28:43 -07:00 |
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Alex Forencich
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b10ff8b4a7
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Unified 10G/25G design for AU250
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2022-03-14 21:39:13 -07:00 |
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