Alex Forencich
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62c2148c8f
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Add pause functionality to FIFO modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-08-14 16:57:16 -07:00 |
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Alex Forencich
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2be72bb758
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Refactor pointer handling in FIFOs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-26 18:47:43 -07:00 |
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Alex Forencich
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9bc052de8b
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Another update to async FIFO timing constraints to deal with OOC clock constraints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-26 14:53:01 -07:00 |
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Alex Forencich
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786e971f40
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Remove separate memory read register (it causes ISE to crash, and is not necessary for URAM inference)
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-12-29 23:54:17 -08:00 |
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Alex Forencich
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46bd4302de
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Update async FIFO timing constraints to handle clocks from OOC IP that are not constrained during synthesis
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-12-08 18:49:21 -08:00 |
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Alex Forencich
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ed6130575d
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Update async FIFO timing constraints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-11-01 23:27:39 -07:00 |
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Alex Forencich
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10e24cc5b1
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Fix timing constraints
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2021-10-13 18:07:45 -07:00 |
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Alex Forencich
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4f1eabab17
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Split async FIFO resets
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2021-10-13 14:05:13 -07:00 |
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Alex Forencich
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e9f7723312
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Reorganize timing constraints
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2021-05-16 23:28:00 -07:00 |
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