232 Commits

Author	SHA1	Message	Date
Alex Forencich	db56c938bf	Replace generate with assign	2019-12-17 00:09:38 -08:00
Alex Forencich	e9c1c5a49d	Fix state register width	2019-08-12 15:12:21 -07:00
Alex Forencich	e9949f57a9	Remove extraneous code	2019-08-05 13:27:12 -07:00
Alex Forencich	562e713837	Remove extraneous connections	2019-07-25 15:34:32 -07:00
Alex Forencich	ab77ac3858	Fix width	2019-07-19 18:16:07 -07:00
Alex Forencich	451db171d1	Don't leave output floating	2019-07-19 18:13:30 -07:00
Alex Forencich	16d1662d98	Add PTP timestamping infrastructure to 10G MACs	2019-07-18 23:13:46 -07:00
Alex Forencich	16755720d3	Add PTP tag inserter module	2019-07-18 22:39:50 -07:00
Alex Forencich	b26f923c2f	Reset synchronizers	2019-07-18 18:35:30 -07:00
Alex Forencich	adb9c4d147	Fix initial values	2019-07-18 18:35:11 -07:00
Alex Forencich	3bd7be44fa	Update FIFO instances and update MACs to use combined FIFO adapter module	2019-07-18 16:25:49 -07:00
Alex Forencich	4da1a83052	Constant FIFO depth	2019-07-17 23:36:10 -07:00
Alex Forencich	1279dcbf47	Back out previous change	2019-07-15 18:09:14 -07:00
Alex Forencich	cc1ff34f53	Add 64 bit timestamp support to ptp_clock_cdc	2019-07-15 16:36:02 -07:00
Alex Forencich	31cb54e67e	Make old icarus verilog happy	2019-07-15 16:15:50 -07:00
Alex Forencich	9d553f2ad4	Also need to use tready	2019-07-15 15:24:12 -07:00
Alex Forencich	d88ada105d	Add PTP TS extract module	2019-07-15 15:17:58 -07:00
Alex Forencich	77bae7a77e	Add PTP clock CDC module and testbench	2019-07-15 15:16:17 -07:00
Alex Forencich	fdfb517761	Add PTP perout module and testbench	2019-06-27 01:30:18 -07:00
Alex Forencich	df04d7e68d	CRC handling logic optimizations	2019-06-20 18:10:53 -07:00
Alex Forencich	9e7f4a9836	Remove unused state bit	2019-06-20 18:02:15 -07:00
Alex Forencich	eb1f38a749	More critical path optimizations	2019-06-19 15:06:55 -07:00
Alex Forencich	134ce04777	Add configurable serdes pipeline register chain	2019-06-19 00:57:28 -07:00
Alex Forencich	303dec8165	Sum errors across data and header	2019-06-19 00:25:41 -07:00
Alex Forencich	1d3554c37e	Rework pointer handling to improve timing	2019-06-16 23:53:26 -07:00
Alex Forencich	7ec836baf6	IP header checksum optimizations	2019-06-16 22:01:11 -07:00
Alex Forencich	b17966f73d	store_last_word timing optimization	2019-06-16 20:01:08 -07:00
Alex Forencich	55bf44117b	shift_axis_extra_cycle timing optimization	2019-06-16 19:57:52 -07:00
Alex Forencich	3b959b2765	CRC handling logic optimizations	2019-06-16 17:39:28 -07:00
Alex Forencich	320a45c4ab	Remove unused state bit	2019-06-16 17:33:14 -07:00
Alex Forencich	8bb243cd35	MAC termination detect timing optimizations	2019-06-16 15:44:41 -07:00
Alex Forencich	4f97303e44	Remove unused code	2019-06-16 15:38:35 -07:00
Alex Forencich	938479c246	MAC RX timing optimizations	2019-06-16 00:36:50 -07:00
Alex Forencich	3684ccafb2	Make use of blocking statements consistent	2019-06-15 16:56:45 -07:00
Alex Forencich	ce13522085	Implement ARP cache clear	2019-06-14 00:01:13 -07:00
Alex Forencich	b41ab00381	Initialize ARP cache	2019-06-13 23:45:17 -07:00
Alex Forencich	296744b37e	Make use of blocking statements consistent	2019-06-12 23:31:03 -07:00
Alex Forencich	6eff2f0030	Decouple transmit PTP tag enable and transmit PTP timestamp enable	2019-06-09 22:03:24 -07:00
Alex Forencich	2794c315e8	Fix synthesizer complaints	2019-06-08 17:36:09 -07:00
Alex Forencich	82fe5a6bdd	Add PTP timestamp capture logic to MACs	2019-06-07 16:38:36 -07:00
Alex Forencich	659aa67481	Pack start packet strobes into the same signal	2019-06-06 17:13:14 -07:00
Alex Forencich	e181ea5abc	Add PTP clock module and testbench	2019-06-03 19:00:28 -07:00
Alex Forencich	3da3725429	Disable bit slipping when RX PRBS check is enabled	2019-05-16 23:22:47 -07:00
Alex Forencich	79ec137243	Add PRBS31 generation and checking to 10G PHY	2019-05-10 20:28:45 -07:00
Alex Forencich	b7d297850c	Move 10G PHY interface logic into separate modules	2019-05-10 14:56:18 -07:00
Alex Forencich	696c634726	Add rx_bad_block outputs	2019-04-17 00:16:45 -07:00
Alex Forencich	1bec485766	Fix constants	2019-04-03 11:48:09 -07:00
Alex Forencich	8e2d936884	Add MII PHY interface, MAC wrappers, and testbenches	2019-03-28 19:18:03 -07:00
Alex Forencich	8285f94eaa	Rename tx_sync regs	2019-03-28 16:27:33 -07:00
Alex Forencich	3eaed305f5	Connect TX underflow status outputs	2019-03-28 16:27:15 -07:00