46 Commits

Author	SHA1	Message	Date
Alex Forencich	2cc3dbd5cc	Update DRP info	2022-03-02 23:12:02 -08:00
Alex Forencich	348aae9687	Update fb2CG@KU15P designs to use new wrapper	2022-03-02 17:38:47 -08:00
Alex Forencich	3997e0d95b	Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter	2022-02-15 18:01:43 -08:00
Alex Forencich	b7bc240aa6	Add JTAG and GPIO passthroughs to application section	2022-01-27 23:06:05 -08:00
Alex Forencich	aab30c8cd0	Add transceiver quad wrappers	2022-01-16 18:28:22 -08:00
Alex Forencich	ce21774f06	Register space reorganization	2021-12-29 22:31:46 -08:00
Alex Forencich	886111c9e6	Update 10G designs for PTP separate RX clock	2021-11-19 01:52:23 -08:00
Alex Forencich	2f5c15f513	Rework GT instances in fb2CG@KU15P 10G and 25G designs	2021-10-21 16:31:36 -07:00
Alex Forencich	7ac4797336	Add default_nettype none and resetall directives	2021-10-20 21:53:39 -07:00
Alex Forencich	607257d7bb	Fix connections	2021-10-20 20:43:11 -07:00
Alex Forencich	6a44a59b2c	Move LED assignments	2021-09-10 10:53:41 -07:00
Alex Forencich	d24c53a2ad	Add application section	2021-09-09 16:01:26 -07:00
Alex Forencich	c920272e84	Use interface address widths directly instead of BAR size parameters	2021-09-08 14:51:18 -07:00
Alex Forencich	cef144e376	Expose DMA_LEN_WIDTH and DMA_TAG_WIDTH parameters	2021-09-08 00:18:11 -07:00
Alex Forencich	bdd2312ecc	More descriptive parameter and signal names for AXI lite control connections	2021-09-07 01:35:15 -07:00
Alex Forencich	8cf16c182b	More descriptive parameter names (SYNC instead of INT)	2021-09-07 01:29:35 -07:00
Alex Forencich	15dec9458a	Add statistics counter subsystem	2021-09-05 23:03:22 -07:00
Alex Forencich	ef00d5ccfd	Add parameters for FIFO output pipeline register depth	2021-09-02 14:45:18 -07:00
Alex Forencich	09a10fc3ca	Fix MAC clock period parameters	2021-09-01 02:06:25 -07:00
Alex Forencich	9295184e19	Fix signal width parametrization	2021-09-01 01:59:42 -07:00
Alex Forencich	37a558e4f6	Add pipeline FIFOs	2021-08-31 22:30:45 -07:00
Alex Forencich	1fc991fc05	Convert fb2CG designs to use common core modules	2021-08-31 21:33:49 -07:00
Alex Forencich	d46cb16dbf	Add scheduler block	2021-08-30 01:28:55 -07:00
Alex Forencich	f71d28c6d8	Normalize RAM size and max frame size	2021-08-20 21:18:44 -07:00
Alex Forencich	34150323df	Remove obsolete packet table size parameters	2021-08-20 18:15:06 -07:00
Alex Forencich	38f766646b	Connect flow control signals to pcie_us_if	2021-08-12 00:05:43 -07:00
Alex Forencich	6517d43ee7	Add missing connection	2021-08-11 23:52:44 -07:00
Alex Forencich	a19474f9dd	Use AXI lite crossbar	2021-08-11 01:31:34 -07:00
Alex Forencich	0b65a1271a	Use new PCIe DMA modules	2021-08-04 01:20:57 -07:00
Alex Forencich	e0e34a9f0d	Update designs for PCIe module changes	2021-08-02 23:04:52 -07:00
Alex Forencich	0a7f1ccbbe	Remove string parameters	2021-06-02 18:18:23 -07:00
Alex Forencich	c7896bef92	Use correct assignment type	2021-03-30 21:50:25 -07:00
Alex Forencich	1aeeb0bbe2	Update designs for PTP CDC and Ethernet MAC module changes	2021-03-30 16:41:31 -07:00
Alex Forencich	d416e9f7fa	Roll back PCIe tag count to 64	2021-03-05 14:04:52 -08:00
Alex Forencich	705133bf7a	Add SPI interface to Gecko BMC on fb2CG@KU15P	2021-03-04 22:34:52 -08:00
Alex Forencich	d0b19efce5	Reconcile PCIe changes	2021-03-01 00:25:15 -08:00
Alex Forencich	a3c104f7dd	Connect write done signals	2021-02-24 15:07:26 -08:00
Alex Forencich	151ed7e179	Add extra reset registers	2021-01-31 11:10:03 -08:00
Alex Forencich	91edbbf3dc	Rename port and interface modules	2020-11-26 15:05:59 -08:00
Alex Forencich	53f4275ea2	Add output registers for I2C interface to improve timing	2020-10-13 23:52:52 -07:00
Alex Forencich	d6810db7f5	Add extra output register for flash interface to improve routability and timing	2020-10-08 19:22:28 -07:00
Alex Forencich	b140d73660	Add PTP perout support to fb2CG@KU15P	2020-10-06 14:51:16 -07:00
Alex Forencich	9c25a4523e	Add QSPI flash access and IPROG for fb2CG	2020-09-29 21:08:21 -07:00
Alex Forencich	6229e73044	Add missing i2c connections	2020-09-25 16:40:31 -07:00
Alex Forencich	94c2861de7	Use correct init_clk frequency	2020-09-23 14:25:48 -07:00
Alex Forencich	1cd406f56f	Add 10G mqnic design for fb2CG@KU15P	2020-09-22 23:10:53 -07:00