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Author SHA1 Message Date
Alex Forencich
82d0770daf Remove unused constraints file 2021-08-31 23:33:00 -07:00
Alex Forencich
c3d498101b Clarify widths 2021-08-31 23:32:42 -07:00
Alex Forencich
37a558e4f6 Add pipeline FIFOs 2021-08-31 22:30:45 -07:00
Alex Forencich
1fc991fc05 Convert fb2CG designs to use common core modules 2021-08-31 21:33:49 -07:00
Alex Forencich
915a915d6e Enable PCIe flow control in core tests 2021-08-31 20:38:08 -07:00
Alex Forencich
bd3fa6abfd Update vivado.mk 2021-08-31 20:03:33 -07:00
Alex Forencich
a5519cd607 Default to US+ configuration 2021-08-31 18:57:32 -07:00
Alex Forencich
bdbdc11841 Initial commit of core logic 2021-08-31 18:42:19 -07:00
Alex Forencich
9731ea5188 Add new PTP subsystem 2021-08-31 01:39:19 -07:00
Alex Forencich
cef2602efe Reorganize address space to place port registers in interface register space 2021-08-30 01:29:25 -07:00
Alex Forencich
d46cb16dbf Add scheduler block 2021-08-30 01:28:55 -07:00
Alex Forencich
d8615468e9 merged changes in eth 2021-08-30 01:28:13 -07:00
Alex Forencich
cee999a201 merged changes in axi 2021-08-30 01:28:08 -07:00
Alex Forencich
454d237ab2 Rename parameter 2021-08-30 01:27:53 -07:00
Alex Forencich
5f7b0292fc Print more PCIe information 2021-08-30 01:27:25 -07:00
Alex Forencich
a6a9a2ebd8 Update readme 2021-08-29 19:16:43 -07:00
Alex Forencich
5c2c6fd2bb Add AXI lite register interface modules 2021-08-29 19:09:52 -07:00
Alex Forencich
3db970636c merged changes in axis 2021-08-27 15:28:53 -07:00
Alex Forencich
6bcd96fa83 Bypass pipeline FIFO when length is zero 2021-08-27 13:54:14 -07:00
Alex Forencich
6b108481b8 Update interconnect address handling 2021-08-26 16:48:31 -07:00
Alex Forencich
e7de9b6ee6 Update PTP CDC instances 2021-08-26 01:07:56 -07:00
Alex Forencich
77938fa422 Update MAC modules for changes in FIFO modules 2021-08-26 00:55:12 -07:00
Alex Forencich
5273a8dda6 merged changes in axis 2021-08-26 00:14:22 -07:00
Alex Forencich
a613cc8a31 Fix alignment 2021-08-25 23:58:52 -07:00
Alex Forencich
6d70b0249e Update readme 2021-08-25 23:58:33 -07:00
Alex Forencich
6a030f5d5e Add axis_pipeline_fifo 2021-08-25 23:54:30 -07:00
Alex Forencich
92681fad8c Add DROP_OVERSIZE_FRAME parameter 2021-08-25 22:56:22 -07:00
Alex Forencich
0b2066abe3 Fix corner case with back-to-back single-cycle transfers 2021-08-25 19:19:30 -07:00
Alex Forencich
f71d28c6d8 Normalize RAM size and max frame size 2021-08-20 21:18:44 -07:00
Alex Forencich
4ceefa376a Normalize FIFO size to 32K 2021-08-20 21:17:41 -07:00
Alex Forencich
34150323df Remove obsolete packet table size parameters 2021-08-20 18:15:06 -07:00
Alex Forencich
8bf38e20c7 Add missing includes 2021-08-20 18:08:22 -07:00
Alex Forencich
43364943e1 merged changes in pcie 2021-08-20 16:10:32 -07:00
Alex Forencich
6af4461705 Fix length register widths and max value handling 2021-08-20 16:09:58 -07:00
Alex Forencich
0563eb4727 Check MSBs 2021-08-20 14:12:26 -07:00
Alex Forencich
85391d2b9b Compare all fields 2021-08-20 14:10:03 -07:00
sungsoo.han
ceeea4b451 modify acknowledge assign 2021-08-17 16:42:26 +09:00
sungsoo.han
edaec3bd38 add LAST_ENABLE to axis_arb_mux 2021-08-17 16:00:23 +09:00
Alex Forencich
84e19ca305 Update file lists 2021-08-16 18:12:19 -07:00
Alex Forencich
fb241ae992 merged changes in pcie 2021-08-16 18:06:46 -07:00
Alex Forencich
943731d624 Use new modules in dma_if_mux modules 2021-08-16 18:04:38 -07:00
Alex Forencich
292f73f43d Add DMA RAM demux modules 2021-08-16 18:03:38 -07:00
Alex Forencich
1342e31976 Add DMA IF descriptor mux module 2021-08-16 18:03:22 -07:00
Alex Forencich
14c84088ee Reorganize driver code 2021-08-13 14:22:32 -07:00
Alex Forencich
38f766646b Connect flow control signals to pcie_us_if 2021-08-12 00:05:43 -07:00
Alex Forencich
6517d43ee7 Add missing connection 2021-08-11 23:52:44 -07:00
Alex Forencich
09c90e321b merged changes in pcie 2021-08-11 23:38:41 -07:00
Alex Forencich
7810b3c99e Connect RQ sequence number ports in pcie_us_if testbench 2021-08-11 19:53:28 -07:00
Alex Forencich
7fed6876a3 Init seq to 0 2021-08-11 19:52:47 -07:00
Alex Forencich
ac96ae97d3 Add flow control signals to pcie_us_if 2021-08-11 19:37:51 -07:00