FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity
2,346 Commits 1 Branch 0 Tags
Commit Graph

2346 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Joachim Foerster
60c2b6745d modules/mqnic/: Fix and enhance Makefile 
- Apply "Shared Makefile" style as found in [1]
- Especially but not only for cross compilation:
  - Accept commonly used variable KDIR to specify kernel build directory
  - Additionally accept KERNEL_SRC (instead of KDIR) as used by PetaLinux/Yocto
- Route all usual external module targets through to Kbuild
- Provide "install" target as shortcut for module installation
- Use $(MAKE) as recommended in [2]

[1] https://www.kernel.org/doc/html/latest/kbuild/modules.html, section 3.1
[2] https://www.gnu.org/software/make/manual/make.html#MAKE-Variable, section 5.7.1.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2021-12-15 23:29:02 -08:00
Joachim Foerster
6b1666e3b8 modules/mqnic/: Add ignore file 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2021-12-15 23:29:02 -08:00
Joachim Foerster
2390ac9a23 utils/: Fix and enhance Makefile 
Not only for typical cross-compilation build environments:

- allow to use CC definition from build environment
- ditto for PREFIX, packaging typically wants to use /usr
- use CPPFLAGS for include paths and just append
- let build environment decide about things like -Ox,
  append rest of flags to CFLAGS
- use LDFLAGS, typically set by build environment

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2021-12-15 23:29:02 -08:00
Joachim Foerster
b79487dbf3 utils/: Ignore mqnic-bmc executable 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2021-12-15 23:29:02 -08:00
Alex Forencich
22a27a479c Configure port RSS settings 2021-12-12 17:44:39 -08:00
Alex Forencich
11f31c896c Split interface from net_device 2021-12-12 17:28:43 -08:00
Alex Forencich
2f70a871a7 Minor refactor 2021-12-12 14:21:13 -08:00
Alex Forencich
a53d3acd3f Pass CQ ring instead of index 2021-12-12 14:20:56 -08:00
Alex Forencich
6117f85656 Ensure one-to-one mapping of queues to CQs 2021-12-12 14:20:05 -08:00
Alex Forencich
56706beefc Pass EQ ring instead of index 2021-12-12 13:58:26 -08:00
Alex Forencich
0418fe33a6 Rename ring_index to index 2021-12-12 13:46:09 -08:00
Alex Forencich
413238f81c Refactor interrupt handling 2021-12-12 13:34:33 -08:00
Alex Forencich
3c6f80b80c Add dev references to CQ and EQ rings 2021-12-12 01:53:38 -08:00
Alex Forencich
bfc8e959bf Split ring buffer allocation from ring creation 2021-12-12 01:52:24 -08:00
Alex Forencich
eeedc179fb Unconditionally deactivate rings 2021-12-12 01:42:14 -08:00
Alex Forencich
292d805450 Rename mqnic_priv.ports to mqnic_priv.port 2021-12-12 01:38:45 -08:00
Alex Forencich
630d5a565d Disambiguate rings 2021-12-12 01:37:55 -08:00
Alex Forencich
b340d2aed0 Use min_t for range enforcement 2021-12-11 01:37:59 -08:00
Alex Forencich
53dfd68338 Use MQNIC_MAX_IRQ define when allocating MSI IRQs 2021-12-11 01:27:44 -08:00
Alex Forencich
74bb15bf00 Use ring indicies during setup 2021-12-10 21:05:57 -08:00
Alex Forencich
ddeb8bad94 Use atomic notifier chain for interrupt handling 2021-12-10 21:05:31 -08:00
Alex Forencich
5e65a384e2 Track ring active state 2021-12-10 21:04:52 -08:00
Alex Forencich
c9de7d24d0 Normalize ring_index parameter 2021-12-10 21:03:46 -08:00
Alex Forencich
32a82929c6 Normalize create/destroy methods 2021-12-10 21:02:57 -08:00
Alex Forencich
ed36f169f9 Rename mqnic_priv.port to mqnic_priv.index 2021-12-10 21:01:51 -08:00
Alex Forencich
c739b05b69 Remove unnecessary priv parameters 2021-12-10 20:59:44 -08:00
Alex Forencich
7a43618e3c Use start_soon instead of fork 2021-12-10 20:43:21 -08:00
Alex Forencich
ae2f64f6ba merged changes in eth 2021-12-10 18:50:07 -08:00
Alex Forencich
f8a1339581 merged changes in axi 2021-12-10 18:50:04 -08:00
Alex Forencich
b8e55944b1 merged changes in pcie 2021-12-10 18:42:24 -08:00
Alex Forencich
293cfe153c Use start_soon instead of fork 2021-12-10 18:23:39 -08:00
Alex Forencich
1f80696b55 Use start_soon instead of fork 2021-12-10 18:19:11 -08:00
Alex Forencich
49f5507d9e merged changes in axis 2021-12-10 18:17:40 -08:00
Alex Forencich
4df34f1344 Use start_soon instead of fork 2021-12-10 18:16:38 -08:00
Alex Forencich
bac4e4066f Use start_soon instead of fork 2021-12-10 17:44:37 -08:00
Yizhou Shan
29bb1d6cb5 Add some file extentions to gitignore 2021-12-10 13:31:58 -08:00
Ulrich Langenbach
5e708ca4c7 Fix multi-driven net issue when S_RAM_SEL_WIDTH = 0 
the same as fixed in verilog-pcie 3a124837115e51e2273ab7d1c61d80ee01f891c1
in dma_ram_demux_rd.v adapted to module dma_ram_demux_wr.v
 2021-12-10 17:39:49 +01:00
Alex Forencich
161a25b4d5 Add more FPGA JTAG IDs 2021-12-03 00:22:29 -08:00
Alex Forencich
bbb9f42516 merged changes in pcie 2021-12-02 17:00:11 -08:00
Alex Forencich
17d7353523 Indexing updates 2021-12-02 16:59:16 -08:00
Alex Forencich
3a12483711 Fix multi-driven net issue when S_RAM_SEL_WIDTH = 0 2021-12-02 16:50:26 -08:00
Alex Forencich
7e3d8606fc Rework window creation 2021-12-02 16:46:56 -08:00
Alex Forencich
540e7eb1de Fix offset 2021-12-02 16:46:35 -08:00
Alex Forencich
089c405c4f Fix clock connections 2021-11-30 16:39:27 -08:00
Alex Forencich
8674bd1e69 Update app testbench 2021-11-30 15:36:38 -08:00
Alex Forencich
720a06ca8b Update mux instances 2021-11-30 15:36:24 -08:00
Alex Forencich
bbc94af35e merged changes in eth 2021-11-30 14:41:16 -08:00
Alex Forencich
ebd80e7267 Test multiple ports 2021-11-30 14:12:34 -08:00
Alex Forencich
9d817af8d1 Test all interfaces 2021-11-30 00:57:41 -08:00
Alex Forencich
639117e53f Adjust clock connections to improve connection to testbench 2021-11-30 00:16:47 -08:00