Alex Forencich
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835f0d38f0
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Update PTP subsystem to use separate clock for improved stability
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-06 17:46:16 -07:00 |
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Alex Forencich
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c2fea3a616
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Add port register blocks with support for PHY link status reporting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-04 09:03:37 -07:00 |
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Alex Forencich
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cfdd6f5455
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Decouple transmit completion handling from PTP timestamping
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-01 17:41:47 -07:00 |
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Alex Forencich
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7f8bbe30de
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Add application ID
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-21 13:15:45 -07:00 |
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Alex Forencich
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ba70498518
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fpga: Add DMA immediate connections and parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-20 15:00:58 -07:00 |
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Alex Forencich
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eb530475fb
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More expressive flash format register
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-15 18:38:01 -07:00 |
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Alex Forencich
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f687aba432
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fpga/mqnic: Update designs to use port mapping modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-13 01:37:10 -07:00 |
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Alex Forencich
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c5d5fe8a64
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fpga/mqnic: Remove unused wires
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-09 23:02:44 -07:00 |
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Alex Forencich
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f082196b4a
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Expose EVENT_QUEUE_INDEX_WIDTH parameter at top-level
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2022-03-29 23:15:06 -07:00 |
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Alex Forencich
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09128df360
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Add SCHED_PER_IF parameter to split scheduler count from port count
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2022-03-28 15:20:33 -07:00 |
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Alex Forencich
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dfae34ed25
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Pass through PTP pipelining settings
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2022-03-28 00:50:29 -07:00 |
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Alex Forencich
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e95c132045
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Route PCIe user reset through BUFG
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2022-03-25 01:26:29 -07:00 |
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Alex Forencich
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056f78716a
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Add pipeline registers
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2022-03-17 15:39:44 -07:00 |
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Alex Forencich
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202f407686
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Unified 10G/25G design for VCU1525
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2022-03-14 21:39:55 -07:00 |
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