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Author SHA1 Message Date
Alex Forencich
89ee44d410 Add test for PCIe spread spectrum clocking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 22:02:09 -08:00
Alex Forencich
36cf9c9b06 Remove unnecessary shadow valid registers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 14:03:55 -08:00
Alex Forencich
be0d9b7b88 Improve handling of instance name mangling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 13:37:25 -08:00
Alex Forencich
5560fa2b32 Fix timestamp capture/sync logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-30 14:05:16 -08:00
Alex Forencich
16cd84123d Add user_sma_clk pins to VCU108 and VCU118 constraints files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-29 13:58:22 -08:00
Alex Forencich
7f9fed6f84 Update readme 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-10 16:56:42 -08:00
Alex Forencich
3535e53746 Add example design for Alveo U55C and Alveo U55N/Varium C1100 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-10 15:40:14 -08:00
Alex Forencich
fe5f6aa3f5 Merge AU50 into Alveo example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-10 15:32:38 -08:00
Alex Forencich
de818ad621 Merge AU280 into Alveo example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-10 15:30:37 -08:00
Alex Forencich
58732ebeb3 Rework Alveo parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-10 15:25:38 -08:00
Alex Forencich
0986d1e901 Rework 7132 parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-08 13:36:21 -08:00
Alex Forencich
1b29a88b18 Rename AU200 to Alveo 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-08 11:50:50 -08:00
Alex Forencich
bd8e8e5b20 Add PTP time distribution components 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 13:07:15 -08:00
Alex Forencich
009560f583 Use latest version of cocotbext-eth 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 12:18:46 -08:00
Alex Forencich
01badce3a1 Remove unnecessary resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-01 18:30:32 -07:00
Alex Forencich
49513b45d4 Merge AU200, AU250, and VCU1525 designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-12 22:51:07 -07:00
Alex Forencich
e84da8dbfb Update HTG-9200 readmes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-26 23:12:52 -07:00
Alex Forencich
b5d1fadb7e Add makefiles for VU13P variant of HTG-9200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-26 15:07:16 -07:00
Alex Forencich
5ff1e17a29 Add missing assign to frame_min_count_reg in axis_baser_tx_64 module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-24 13:35:29 -07:00
Alex Forencich
90e6dfc638 Use phase detector in PTP CDC module for coarse period tuning, use 9 LSBs of timestamp for fine sync to avoid rollover corrections, reduce FNS comparison width to 4 bits 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-23 14:58:44 -07:00
Alex Forencich
a9e3d3cae8 Wait longer to ensure PTP CDC module has fully stabilized in MAC testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-23 14:52:48 -07:00
Alex Forencich
f9ae6da8bd Improve PTP CDC module testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-23 14:33:14 -07:00
Alex Forencich
5a37442706 Merge FNS registers into NS registers in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 22:52:59 -07:00
Alex Forencich
b0a4d75fd9 Remove extraneous code 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 01:08:01 -07:00
Alex Forencich
4a32c86f07 Match integrator width to period register width in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 01:07:43 -07:00
Alex Forencich
cf441f004d Rename source sync signals in PTP CDC module for consistency 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 01:07:12 -07:00
Alex Forencich
4b1f48ab5b Parameter clean-up in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-21 16:34:05 -07:00
Alex Forencich
aad30d09a1 Make FNS_WIDTH an internal parameter in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-21 16:30:29 -07:00
Alex Forencich
98b4fbb56d Remove USE_SAMPLE_CLOCK parameter in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-18 16:58:02 -07:00
Alex Forencich
060e55b915 Wait for correct PTP CDC instance to lock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-18 16:39:30 -07:00
Alex Forencich
b316c6764e Use quad wrappers in ExaNIC X25 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 12:44:50 -07:00
Alex Forencich
f9eda00d68 Use quad wrappers in ExaNIC X10 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 12:43:29 -07:00
Alex Forencich
dc58b2447f Use quad wrappers in ZCU102 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 12:42:39 -07:00
Alex Forencich
d5df47d8b0 Use quad wrappers in ZCU106 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 12:42:04 -07:00
Alex Forencich
4618edcd8e Use quad wrappers in VCU108 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:15:29 -07:00
Alex Forencich
72de6c653a Use quad wrappers in AU50 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:09:00 -07:00
Alex Forencich
66987c8f62 Use quad wrappers in AU280 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:08:32 -07:00
Alex Forencich
22f327b35f Use quad wrappers in AU250 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:07:30 -07:00
Alex Forencich
65361d157b Use quad wrappers in AU200 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:06:28 -07:00
Alex Forencich
bd06e57764 Use quad wrappers in VCU1525 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:05:23 -07:00
Alex Forencich
c673ddbc14 Use quad wrappers in fb2CG@KU15P example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 00:37:44 -07:00
Alex Forencich
5d61059488 Use quad wrappers in ADM-PCIE-9V3 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 00:36:39 -07:00
Alex Forencich
1e88ed3d2e Update readme 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 23:12:59 -07:00
Alex Forencich
68736d02ae Add 10G/25G design for Arista 7132LB-48Y4C switch 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 23:06:49 -07:00
Alex Forencich
351ec79fef Use quad wrappers in VCU118 example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 01:27:53 -07:00
Alex Forencich
75c2cc0acc Use quad wrappers in HTG9200 example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 01:24:26 -07:00
Alex Forencich
aaeeb05ac0 Fix PHY configuration connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 00:09:38 -07:00
Alex Forencich
fa05d4ff3c Add TX and RX enable inputs to MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-24 01:24:33 -07:00
Alex Forencich
20c542051d Use cfg prefix for configuration signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-22 17:14:52 -07:00
Alex Forencich
f92a94d278 merged changes in axis 2023-08-16 16:19:04 -07:00