330 Commits

Author	SHA1	Message	Date
Alex Forencich	b691a30760	Accept OS_START block type	2019-03-26 12:06:58 -07:00
Alex Forencich	9891d75c2f	Fix STATE_WAIT_END	2019-03-25 23:24:01 -07:00
Alex Forencich	0efb135b7a	Fix STATE_WAIT_END	2019-03-25 15:06:45 -07:00
Alex Forencich	fb4abb6b39	Fix widths	2019-03-14 14:44:00 -07:00
Alex Forencich	ec38440d89	Add 10G Ethernet MAC/PHY combination modules and testbenches	2019-01-31 18:13:07 -08:00
Alex Forencich	e644ce3895	Add start packet strobe timing outputs to MAC modules	2019-01-31 17:00:23 -08:00
Alex Forencich	9ae60dcd9a	Simplify lane swapping code	2019-01-22 14:22:01 -08:00
Alex Forencich	54e31c51b7	Adjustment to scrambler bypass	2019-01-22 14:21:14 -08:00
Alex Forencich	6238ed5755	Report error for invalid encoding	2019-01-22 14:19:43 -08:00
Alex Forencich	e784900050	Remove unused code	2019-01-22 14:18:27 -08:00
Alex Forencich	dbbbc28059	Add 10G Ethernet PHY modules and testbenches	2019-01-16 18:00:56 -08:00
Alex Forencich	91553e6edf	Add XGMII 10GBASE-R encoder and decoder modules and testbenches	2019-01-16 17:30:07 -08:00
Alex Forencich	ea02b6c898	Properly handle short IFG	2019-01-16 13:26:47 -08:00
Alex Forencich	32d889b20d	Remove unreachable code	2019-01-16 13:26:14 -08:00
Alex Forencich	6b85aed564	Any control characters in packet considered an error	2018-11-08 13:34:32 -08:00
Alex Forencich	ebe31e811c	Use parameters for control characters	2018-11-08 13:15:47 -08:00
Alex Forencich	6b1b36ded6	Assert header ready earlier if possible	2018-11-07 23:10:07 -08:00
Alex Forencich	b223c94adb	Use registered header	2018-11-07 23:08:40 -08:00
Alex Forencich	d2fedc4134	Rename ports	2018-11-07 22:35:06 -08:00
Alex Forencich	98fc042489	Convert generated udp_demux to verilog parametrized module	2018-11-02 00:39:52 -07:00
Alex Forencich	81e9aa0c77	Convert generated ip_demux to verilog parametrized module	2018-11-02 00:25:23 -07:00
Alex Forencich	18c4214edb	Convert generated eth_demux to verilog parametrized module	2018-11-02 00:23:31 -07:00
Alex Forencich	470ab887d9	Update mux instances	2018-11-01 00:59:14 -07:00
Alex Forencich	fea1186f57	Convert generated udp_arb_mux to verilog parametrized module	2018-11-01 00:48:26 -07:00
Alex Forencich	554e0a5380	Convert generated ip_arb_mux to verilog parametrized module	2018-11-01 00:40:09 -07:00
Alex Forencich	96cefbe0c1	Convert generated eth_arb_mux to verilog parametrized module	2018-10-31 21:42:28 -07:00
Alex Forencich	67025121ab	Convert generated udp_mux to verilog parametrized module	2018-10-31 18:09:44 -07:00
Alex Forencich	f20312b199	Convert generated ip_mux to verilog parametrized module	2018-10-31 18:08:39 -07:00
Alex Forencich	d28d459d70	Convert generated eth_mux to verilog parametrized module	2018-10-31 15:48:12 -07:00
Alex Forencich	ad8828d5b7	Update FIFO instances	2018-10-30 11:58:06 -07:00
Alex Forencich	fe0bf3b7c6	Remove old modules	2018-10-24 01:08:27 -07:00
Alex Forencich	0aca4c7dcc	Update 10G MAC to use new modules	2018-10-24 00:54:41 -07:00
Alex Forencich	de69975872	Add AXI stream XGMII RX and TX modules and testbenches	2018-10-23 23:34:43 -07:00
Alex Forencich	5e12f97518	MAC optimizations	2018-10-19 15:24:33 -07:00
Alex Forencich	5b7646ccda	Rework ARP subsystem	2018-06-18 13:59:58 -07:00
Alex Forencich	25d1b373cc	Use don't care bits	2018-06-14 15:20:20 -07:00
Alex Forencich	fea477db09	Add unused ports	2018-06-11 16:36:44 -07:00
Alex Forencich	3ae97c71a0	Add documentation	2018-06-04 18:21:55 -07:00
Alex Forencich	e95b39b36d	Update iddr/oddr Altera device support	2018-06-04 18:20:31 -07:00
Alex Forencich	6727e5a0bd	Happy new year	2018-02-27 01:47:56 -08:00
Alex Forencich	0fd157964a	Happy new year	2018-02-26 12:50:51 -08:00
Alex Forencich	bd27156f35	AXI stream updates	2018-02-26 00:08:08 -08:00
Alex Forencich	77211926f2	Fix classifier logic	2017-06-09 21:27:29 -07:00
Alex Forencich	9a507b388d	Update LFSR module	2017-06-09 21:17:28 -07:00
Alex Forencich	a3b5d5d167	Update RGMII PHY interface and add RGMII MAC wrappers	2017-05-31 18:40:49 -07:00
Alex Forencich	bb9e789645	Update GMII PHY interface and add GMII MAC wrappers	2017-05-31 18:40:18 -07:00
Alex Forencich	8ff4312601	Update MAC modules to use new modules	2017-05-31 18:37:33 -07:00
Alex Forencich	817e7c2667	Add AXI stream GMII RX and TX modules and testbenches	2017-05-31 16:11:20 -07:00
Alex Forencich	9b2ac9dfc1	Happy new year	2017-05-18 13:47:45 -07:00
Alex Forencich	270641b7a3	Update UDP modules and example designs to utilize UDP checksum modules	2016-09-30 22:15:21 -07:00