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Author SHA1 Message Date
Alex Forencich
74f4c6fc2d Support using separate clock for PTP timestamps on RX path 2021-11-18 23:56:51 -08:00
Alex Forencich
af3b6312a9 Add PTP_USE_SAMPLE_CLOCK parameter to testbenches 2021-11-18 21:12:06 -08:00
Alex Forencich
a2e2919add Update readme 2021-11-18 16:34:43 -08:00
Alex Forencich
d1210d02a3 Add example design for ZCU106 2021-11-18 16:33:39 -08:00
Alex Forencich
0830ca6a7a Add example design for VCU1525 2021-11-18 16:32:38 -08:00
Alex Forencich
fb4b32fba0 Add example design for VCU118 2021-11-18 16:31:55 -08:00
Alex Forencich
cef69d1e1f Add example design for VCU108 2021-11-18 16:31:18 -08:00
Alex Forencich
6740ddafaf Add example design for ExaNIC X25 2021-11-18 16:29:52 -08:00
Alex Forencich
0cbe4897da Add example design for Alveo U50 2021-11-18 16:28:39 -08:00
Alex Forencich
068ea6edc2 Add example design for Alveo U280 2021-11-18 16:27:48 -08:00
Alex Forencich
12fea955d2 Add example design for Alveo U250 2021-11-18 16:26:43 -08:00
Alex Forencich
6e5f9f33f2 Add example design for Alveo U200 2021-11-18 16:25:59 -08:00
Alex Forencich
fca6341636 Add flash size check for Alveo boards 2021-11-18 16:23:37 -08:00
Alex Forencich
057edebc36 Add example design for ADM-PCIE-9V3 2021-11-18 16:21:28 -08:00
Alex Forencich
9632a40ad7 Parameter cleanup 2021-11-18 14:23:47 -08:00
Alex Forencich
667076ee39 Testbench cleanup 2021-11-18 13:50:32 -08:00
Alex Forencich
a330c6e7f0 Testbench cleanup 2021-11-18 13:45:55 -08:00
Alex Forencich
419ee057c8 Fix instance name 2021-11-18 13:44:46 -08:00
Alex Forencich
c2d2b441fb Add missing symlink 2021-11-17 18:29:26 -08:00
Alex Forencich
605965fec9 Add mqnic core logic module for AXI 2021-11-17 18:16:40 -08:00
Alex Forencich
5bf9de656c Update testbenches 2021-11-17 18:08:40 -08:00
Alex Forencich
dc75f86980 merged changes in pcie 2021-11-17 17:38:57 -08:00
Alex Forencich
6920845989 Update example design testbenches 2021-11-17 17:21:57 -08:00
Alex Forencich
2c3a5f4bda Update testbenches 2021-11-17 17:21:35 -08:00
Alex Forencich
63e7df0044 Fix makefile 2021-11-17 16:43:27 -08:00
Alex Forencich
78badc447f Update pcie_if model 2021-11-17 01:00:24 -08:00
Alex Forencich
e898f7bdc2 Accept any completion status-related DMA error 2021-11-16 00:54:52 -08:00
Alex Forencich
0d1af9ba55 Use correct completer IDs 2021-11-16 00:44:36 -08:00
Alex Forencich
6cafb46c49 Include TLP in log messages 2021-11-16 00:33:44 -08:00
Alex Forencich
b3145508ed Remove debug code 2021-11-16 00:10:50 -08:00
Alex Forencich
b64269c2e7 Fix widths 2021-11-16 00:10:10 -08:00
Alex Forencich
7c511ef1a9 Clean up signal names 2021-11-16 00:09:55 -08:00
Alex Forencich
f40e68350c Remove deprecated assigments 2021-11-15 14:39:47 -08:00
Alex Forencich
fbb507be82 Remove deprecated assigments 2021-11-15 14:31:28 -08:00
Alex Forencich
5b528158df Remove deprecated assignments 2021-11-09 11:55:12 -08:00
Alex Forencich
8a7f410aaf Don't read address/data if valid is not set 2021-11-07 19:03:10 -08:00
Alex Forencich
8bd6c8ea34 Remove some lint 2021-11-07 18:23:13 -08:00
Alex Forencich
32d99b4dd9 Use constants from cocotbext-eth 2021-11-07 18:21:06 -08:00
Alex Forencich
078bbc8f07 Fix typos 2021-11-07 17:50:23 -08:00
Alex Forencich
76e18d2af8 Add 10G mqnic design for Stratix 10 MX dev kit 2021-11-07 13:59:05 -08:00
Alex Forencich
bd8a0513ed Add mqnic core logic for Stratix 10 GX/SX/TX/MX 2021-11-07 13:28:12 -08:00
Alex Forencich
dfdf880c3a Add Stratix 10 JTAG IDs 2021-11-06 16:20:54 -07:00
Alex Forencich
7ab18f8602 Increase event FIFO depth 2021-11-06 16:14:49 -07:00
Alex Forencich
fb0f6f67f7 Remove debug code 2021-11-06 16:14:32 -07:00
Alex Forencich
f8a24d1c46 Add attributes to RAMs for proper synthesis in Quartus 2021-11-06 16:14:22 -07:00
Alex Forencich
cefb4568e7 merged changes in axi 2021-11-06 15:22:50 -07:00
Alex Forencich
b4bdfb6542 Add FIFO output register in AXI lite crossbar modules 2021-11-06 15:20:19 -07:00
Alex Forencich
0b16849b57 Add attributes to RAMs for proper synthesis in Quartus 2021-11-04 20:43:13 -07:00
Alex Forencich
aa89471cca Add bus_num port to mqnic_core_pcie 2021-11-03 21:40:19 -07:00
Alex Forencich
e0cfb0c107 merged changes in pcie 2021-11-03 20:47:25 -07:00