FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity
280 Commits 1 Branch 0 Tags
Commit Graph

280 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Alex Forencich
8cfbe18335 Use FIFO for op tag management in PCIe read DMA modules 2021-02-25 16:30:23 -08:00
Alex Forencich
41d0e7cb7e Minor optimization 2021-02-24 14:48:14 -08:00
Alex Forencich
63006e8092 Add output FIFO to DMA IF mux for read response data 2021-02-24 13:54:40 -08:00
Alex Forencich
ed29997a59 Add write done tracking to DMA IF mux 2021-02-24 13:51:50 -08:00
Alex Forencich
6fb2eb6b4e Remove unnecessary delays from testbenches 2021-02-24 13:50:45 -08:00
Alex Forencich
40a191a06d Add output FIFO and write done tracking to ultrascale PCIe read DMA interface 2021-02-24 13:50:05 -08:00
Alex Forencich
9c8417799d Add output FIFO and write done tracking to AXI stream sink DMA client 2021-02-24 13:48:56 -08:00
Alex Forencich
070689692d Add wr_done signal to RAM model and placeholders to DMA components 2021-02-24 13:47:53 -08:00
Alex Forencich
057a93e07a Sync data handling 2021-02-16 13:56:44 -08:00
Alex Forencich
742ef1c272 Add same-width test cases to DMA clients 2021-02-16 01:26:05 -08:00
Alex Forencich
33bc8c21ae Fix bug in DMA client source when AXI stream width matches RAM interface width 2021-02-16 01:25:07 -08:00
Alex Forencich
20b2414d7a Use reg instead of next for read operation generation 2021-02-15 00:09:03 -08:00
Alex Forencich
93e2769269 Make 64-bit-only states no-ops for other interface widths 2021-02-14 15:17:28 -08:00
Alex Forencich
a78674c06a Refactor TLP header and tuser computation 2021-02-14 11:16:25 -08:00
Alex Forencich
93496729f3 Update testbench 2021-02-12 16:59:13 -08:00
Alex Forencich
fb1d64e710 Add pipeline stage to dma_if_pcie_us_wr 2021-02-12 16:58:35 -08:00
Alex Forencich
6d98a7c0e6 Ensure output FIFOs use distributed RAM 2021-02-11 00:14:36 -08:00
Alex Forencich
5f7697178b Remove await ReadOnly 2021-02-10 18:42:32 -08:00
Alex Forencich
ba1b0ef20b Add output FIFO to write DMA interface module 2021-02-10 17:29:17 -08:00
Alex Forencich
f76ed26503 Add output FIFO to AXI stream source DMA client 2021-02-10 17:28:08 -08:00
Alex Forencich
c6d8983fcd Add wr_done output to DMA RAMs 2021-02-07 23:47:46 -08:00
Alex Forencich
633b47ef7f Update XDC files 2021-02-06 17:14:26 -08:00
Alex Forencich
5d91fde42a Update github actions 2021-01-16 13:40:35 -08:00
Alex Forencich
87a6efe05c Rework sim_build output directory, fix default makefile target 2020-12-29 16:26:48 -08:00
Alex Forencich
44bf507e24 Update readme 2020-12-19 14:59:02 -08:00
Alex Forencich
ba50df774d Add Github Actions regression tests 2020-12-19 14:18:05 -08:00
Alex Forencich
8d7f4b52bf Add test durations 2020-12-19 14:17:47 -08:00
Alex Forencich
0e0e9da047 Add tox.ini 2020-12-19 14:11:23 -08:00
Alex Forencich
a0a5ccc0a4 Add cocotb testbenches 2020-12-19 14:10:57 -08:00
Alex Forencich
7c19cb770d Properly name registers, CQ demux bug fix 2020-12-19 14:09:56 -08:00
Alex Forencich
cabad17552 Migrate example design testbenches to cocotb 2020-12-18 22:10:32 -08:00
Alex Forencich
99e91c4d90 Fix pointer handling issue in PCIe AXI DMA write module 2020-12-18 18:37:53 -08:00
Alex Forencich
f567db764b Rewrite 4K address boundary crossing checks 2020-11-11 23:54:39 -08:00
Alex Forencich
5546e40812 Fix user_clk_frequency setting in testbenches 2020-10-12 23:05:28 -07:00
Alex Forencich
d22d3e8bd1 Update VCU118 XDC 2020-10-06 00:40:16 -07:00
Alex Forencich
8f8cb39157 Update flash programming configuration for ExaNIC X10 and X25 2020-10-03 15:26:56 -07:00
Alex Forencich
10a6797d27 Update VCU108 XDC 2020-10-02 20:49:23 -07:00
Alex Forencich
bbe94fd0d3 Fix flash programming commands for VCU108 2020-10-01 00:50:31 -07:00
Alex Forencich
f3c8e47ccc Fix bitstream config for VCU1525 2020-09-30 23:50:03 -07:00
Alex Forencich
3ce28df7e0 Update flash programming commands 2020-09-29 18:28:38 -07:00
Alex Forencich
c04ba2de2e Fix flash settings 2020-09-29 17:30:42 -07:00
Alex Forencich
a2685a102b Update LED driver timing constraints 2020-09-28 17:24:24 -07:00
Alex Forencich
1f93608527 Add fb2CG flash programming commands 2020-09-27 01:47:00 -07:00
Alex Forencich
44955d2010 Make DMA RAM module synchronous and add async variant for improved RAM inference 2020-09-25 21:49:07 -07:00
Alex Forencich
ef2f01bd9f Update XDC 2020-09-23 14:24:42 -07:00
Alex Forencich
4ae9ec818c Add timing constraints for LED driver 2020-09-22 22:13:54 -07:00
Alex Forencich
c7594c77ab Add fb2CG AXI example design 2020-09-20 01:17:52 -07:00
Alex Forencich
722222a01c Add AU250 AXI example design 2020-09-18 14:51:35 -07:00
Alex Forencich
0080f631c6 Add AU200 AXI example design 2020-09-18 14:51:24 -07:00
Alex Forencich
d7f96eb104 Rewrite priority encoder to remove recusive construction 2020-08-17 18:30:40 -07:00