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Commit Graph

44 Commits

Author SHA1 Message Date
Alex Forencich
8ee9805473 Fix organization 2020-10-03 15:50:28 -07:00
Alex Forencich
8dfdf3a717 Add IPROG for ExaNIC X10 2020-10-03 15:36:40 -07:00
Alex Forencich
be67f173b6 Update flash programming configuration for ExaNIC X10 and X25 2020-10-03 15:32:21 -07:00
Alex Forencich
70b7082fb6 Implement new control registers 2020-09-19 17:25:58 -07:00
Alex Forencich
c8f5bb235c Remove extraneous clock connections 2020-08-19 18:33:41 -07:00
Alex Forencich
e54eb685b3 Update makefiles 2020-08-06 18:43:47 -07:00
Alex Forencich
77b9cace47 Update BAR configuration in testbenches 2020-07-28 19:01:53 -07:00
Alex Forencich
ffd04d2bb0 Cleanup 2020-07-28 19:00:33 -07:00
Alex Forencich
d449be8fc5 Convert to 64 bit BARs 2020-07-24 16:54:57 -07:00
Alex Forencich
e230fecb23 XDC clean up 2020-07-13 23:58:39 -07:00
Alex Forencich
f99736d4f5 Convert to TCL IP 2020-07-11 20:07:13 -07:00
Alex Forencich
50af74aa88 Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH 2020-04-20 18:43:26 -07:00
Alex Forencich
9e3e80661c Use common sync_reset module 2020-03-27 23:53:05 -07:00
Alex Forencich
a501f33c09 Update parameters 2019-12-29 16:46:25 -08:00
Alex Forencich
0955a4101f Fix signal widths 2019-12-29 16:45:32 -08:00
Alex Forencich
7a68abbb84 Split control and data descriptor paths to DMA engine 2019-12-13 14:15:25 -08:00
Alex Forencich
88e31d0ccb Connect PCIe credit interface to DMA cores 2019-12-13 12:41:50 -08:00
Alex Forencich
6270278c75 Add RSS support 2019-12-06 14:15:16 -08:00
Alex Forencich
0e7a91d927 Connect RQ sequence number 2019-12-03 18:19:17 -08:00
Alex Forencich
489506e4c0 Add FPGA ID register 2019-11-17 12:46:27 -08:00
Alex Forencich
33be402b16 Update widths 2019-11-14 00:02:10 -08:00
Alex Forencich
f36773660d Set flash ID 2019-11-06 15:05:32 -08:00
Alex Forencich
e43c011e33 Update testbenches 2019-11-05 18:31:41 -08:00
Alex Forencich
736321641f Parametrize addressing 2019-10-31 23:24:42 -07:00
Alex Forencich
8fa7e40507 Use new DMA subsystem 2019-10-17 16:02:14 -07:00
Alex Forencich
9ab0d50c0a Add PCIe interface tuser width parameters 2019-10-05 13:56:24 -07:00
Alex Forencich
9a1a58f608 Add PCIe interface tuser width parameters 2019-10-04 16:51:07 -07:00
Alex Forencich
2c46513837 Update designs 2019-09-23 18:21:54 -07:00
Alex Forencich
835abf9412 Remove pcie_us_axi_master instances and corresponding BAR 2019-09-19 17:31:59 -07:00
Alex Forencich
132d44cd90 Increase crossbar threads count 2019-09-11 18:06:14 -07:00
Alex Forencich
d67c9ff70e Pull out scheduler op table size parameter 2019-08-23 07:44:33 -07:00
Alex Forencich
744ac22c75 Normalize queue op table sizes 2019-08-22 19:19:51 -07:00
Alex Forencich
6a354e7aa3 Normalize descriptor table sizes 2019-08-22 19:03:19 -07:00
Alex Forencich
a4132cfda7 Integrate TX checksum offload 2019-08-22 00:45:09 -07:00
Alex Forencich
5f066b9fcd Adjust ExaNIC board ID to match original PCIe ID 2019-08-19 22:04:10 -07:00
Alex Forencich
94c8dabad6 Rewrite scheduler 2019-08-13 00:45:01 -07:00
Alex Forencich
80f06e1fcc Update testbenches 2019-08-13 00:39:28 -07:00
Alex Forencich
26f6774182 Parameter updates and documentation 2019-07-27 23:47:46 -07:00
Alex Forencich
0a16bb1299 Fix parametrization 2019-07-24 01:45:18 -07:00
Alex Forencich
a6c4b8b1b7 Change board IDs 2019-07-21 15:27:01 -07:00
Alex Forencich
ea7ccd182e Move MAC out of port module 2019-07-19 23:29:03 -07:00
Alex Forencich
9de2101cdc Update ExaNIC X10 testbenches 2019-07-19 18:01:24 -07:00
Alex Forencich
eb92578699 Update FIFO instances 2019-07-19 16:17:36 -07:00
Alex Forencich
1df012a8d4 Add ExaNIC X10 design 2019-07-17 16:57:04 -07:00