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Author SHA1 Message Date
Alex Forencich
ebac1a8be6 Derive length from op_read 2021-10-03 11:51:22 -07:00
Alex Forencich
04a80a4d35 Rework FIFO implementation for pcie_axil_master_minimal 2021-10-03 11:48:47 -07:00
Alex Forencich
85b8231abf Add IO operations to bad ops test for pcie_axil_master_minimal 2021-10-03 11:47:45 -07:00
Alex Forencich
bb74bdf2f7 Update pcie_axil_master module to support arbitrary memory operations 2021-10-03 11:46:55 -07:00
Alex Forencich
eea6b66f3f Add PCIe AXI master modules and testbenches 2021-10-02 00:59:18 -07:00
Alex Forencich
824e9fc758 Resize registers 2021-10-02 00:46:21 -07:00
Alex Forencich
c249081dd2 Use DRIVER_NAME define 2021-10-01 23:45:06 -07:00
Alex Forencich
75905778bc Use DRIVER_NAME define 2021-10-01 23:44:50 -07:00
Alex Forencich
437c69abc4 Call remove from shutdown 2021-10-01 18:25:31 -07:00
Alex Forencich
93aed3ede9 Remove UltraScale specific counters 2021-10-01 18:25:12 -07:00
Alex Forencich
4b59bad937 Print more PCIe information 2021-10-01 17:38:58 -07:00
Alex Forencich
cb52a82498 Remove MODULE_SUPPORTED_DEVICE, which was never implemented and was removed in kernel version 5.12 2021-10-01 17:35:43 -07:00
Alex Forencich
0965c77b8e Remove MODULE_SUPPORTED_DEVICE, which was never implemented and was removed in kernel version 5.12 2021-10-01 17:31:15 -07:00
Alex Forencich
aee1431e74 Remove irrelevant address computation 2021-10-01 15:56:51 -07:00
Alex Forencich
d97ac3105f Convert VCU118 to x16 2021-10-01 15:56:28 -07:00
Alex Forencich
618fdff0b8 Convert ADM_PCIE_9V3 to x16 2021-10-01 15:21:10 -07:00
Alex Forencich
adeb2c6b1c Fix alignment 2021-10-01 13:50:30 -07:00
Alex Forencich
d0705fea9b Minor optimizations to completion TLP size computation logic 2021-10-01 13:00:22 -07:00
Alex Forencich
a7b669e22f Update makefiles 2021-10-01 02:39:15 -07:00
Alex Forencich
c044898ec4 One AXI read burst per completion TLP 2021-10-01 00:20:29 -07:00
Alex Forencich
2984b5b09d Copy pcie_axil_master as pcie_axil_master_minimal 2021-09-30 22:38:28 -07:00
Alex Forencich
e0da1819c4 More tests for pipeline FIFO 2021-09-28 01:18:17 -07:00
Alex Forencich
0b5fc5b0e0 Fix off by one error 2021-09-28 01:17:57 -07:00
Alex Forencich
e48901a588 Reorganize test lists 2021-09-28 01:17:28 -07:00
Alex Forencich
d549267e17 Test async FIFO with different clock periods 2021-09-28 00:29:54 -07:00
Alex Forencich
780406197d Add 25G mqnic design for ExaNIC X25 2021-09-26 18:11:00 -07:00
Alex Forencich
92bb1bda57 Remove unused files 2021-09-26 18:00:36 -07:00
Alex Forencich
45b7e3566c Update readme 2021-09-26 01:16:34 -07:00
Alex Forencich
c8e6484af7 Use correct width for full throughput at 25G 2021-09-26 01:04:40 -07:00
Alex Forencich
f2f19f7174 Update terminology, use byte_lanes instead of byte_width 2021-09-25 22:52:19 -07:00
Alex Forencich
bc8715decc Hold read completions until pending writes complete 2021-09-25 00:46:55 -07:00
Alex Forencich
c8dd50b051 pcie_print_link_status was added in kernel version 4.17 2021-09-24 17:05:35 -07:00
Alex Forencich
39fbc194fd Update makefiles 2021-09-20 18:22:47 -07:00
Alex Forencich
52ba4c40e2 Update readme 2021-09-13 20:40:39 -07:00
Alex Forencich
1bee717bc8 Remove old TDMA variants 2021-09-13 17:20:44 -07:00
Alex Forencich
cc6348653d Add TDMA variants 2021-09-13 17:19:50 -07:00
Alex Forencich
620791e562 Add TDMA testbench 2021-09-13 17:11:39 -07:00
Alex Forencich
df9417454e Improve messages 2021-09-13 16:18:11 -07:00
Alex Forencich
4704115974 Allow boot and reset even if flashing is not supported 2021-09-13 16:17:55 -07:00
Alex Forencich
3d64e5fc30 Retry hot reset a few times if necessary 2021-09-13 13:51:36 -07:00
Alex Forencich
5435db91cb Ensure that boot/reset are skipped if flash update fails 2021-09-13 13:51:06 -07:00
Alex Forencich
dfe0dd38f0 Print out mismatches when verify fails 2021-09-13 13:50:27 -07:00
Alex Forencich
9da588cf73 Add dummy reads for timing 2021-09-13 13:49:29 -07:00
Alex Forencich
e8c28e00cd Update tox configuration 2021-09-13 13:02:17 -07:00
Alex Forencich
f25cfa0982 Update tox configuration 2021-09-13 13:00:03 -07:00
Alex Forencich
875b664c13 Update offset 2021-09-13 12:54:35 -07:00
Alex Forencich
b0bb8d628a Update tox configuration 2021-09-13 01:38:16 -07:00
Alex Forencich
b1596751cf Update NetFPGA SUME design 2021-09-13 01:30:36 -07:00
Alex Forencich
f66f4d7cce Update VCU118 designs 2021-09-13 00:09:23 -07:00
Alex Forencich
bfea350194 Update VCU108 design 2021-09-12 23:17:50 -07:00