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Code Issues Projects Releases Wiki Activity
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Commit Graph

14 Commits

Author SHA1 Message Date
Alex Forencich
8fa7e40507 Use new DMA subsystem 2019-10-17 16:02:14 -07:00
Alex Forencich
89b7eccb38 Missed some changes 2019-09-26 23:51:18 -07:00
Alex Forencich
c6e75b40a1 Don't need AXI DMA unaligned support 2019-09-23 18:11:25 -07:00
Alex Forencich
2325966973 Pull out descriptor and completion handling logic 2019-09-23 18:10:35 -07:00
Alex Forencich
bcfd665823 Connect queue index field in queue operation response 2019-09-01 08:29:22 -07:00
Alex Forencich
d67c9ff70e Pull out scheduler op table size parameter 2019-08-23 07:44:33 -07:00
Alex Forencich
a4132cfda7 Integrate TX checksum offload 2019-08-22 00:45:09 -07:00
Alex Forencich
d977cbdac2 Add feature bits 2019-08-19 23:43:52 -07:00
Alex Forencich
94c8dabad6 Rewrite scheduler 2019-08-13 00:45:01 -07:00
Alex Forencich
d99f40db08 Add port CSRs 2019-08-13 00:27:09 -07:00
Alex Forencich
26f6774182 Parameter updates and documentation 2019-07-27 23:47:46 -07:00
Alex Forencich
ea7ccd182e Move MAC out of port module 2019-07-19 23:29:03 -07:00
Alex Forencich
eb92578699 Update FIFO instances 2019-07-19 16:17:36 -07:00
Alex Forencich
351404813a Add port module 2019-07-17 16:42:39 -07:00