31 Commits

Author	SHA1	Message	Date
Alex Forencich	c65161e696	Remove recursively-expanded macros for module parameters in makefiles ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-02-17 16:04:16 -08:00
Alex Forencich	57803eeeb8	Remove deprecated assignments ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-01-24 15:07:45 -08:00
Alex Forencich	8c3df76b97	Fix signal name ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-12-27 18:26:58 -08:00
Alex Forencich	1f80696b55	Use start_soon instead of fork	2021-12-10 18:19:11 -08:00
Alex Forencich	6b18e56cb1	Add default_nettype none and resetall directives	2021-10-20 17:29:12 -07:00
Alex Forencich	c021d01c26	Update example design readmes	2021-05-04 15:48:12 -07:00
Alex Forencich	77d22bfde0	Rework sim_build output directory, fix default makefile target	2020-12-29 14:47:12 -08:00
Alex Forencich	0359d8d76a	Use absolute path to test directory	2020-12-28 19:25:59 -08:00
Alex Forencich	079d6329cb	Migrate example design testbenches to cocotb	2020-12-28 01:11:03 -08:00
Alex Forencich	220e04d1a7	Update example design	2020-12-25 01:47:01 -08:00
Alex Forencich	27ed447005	Use common sync_reset module files	2020-03-27 18:27:45 -07:00
Alex Forencich	a55c354924	Parametrize Ethernet frame parsing	2020-02-21 21:37:57 -08:00
Alex Forencich	4ac6d6803b	Parametrize ARP components	2020-02-20 16:49:47 -08:00
Alex Forencich	c5e886769a	Fix typo	2019-07-19 10:29:55 -07:00
Alex Forencich	16e5ec2106	Update example designs	2019-07-18 17:13:47 -07:00
Alex Forencich	0a6bee6d69	Update example designs	2018-11-08 09:17:29 -08:00
Alex Forencich	7d6889add6	Update example designs	2018-10-30 21:32:32 -07:00
Alex Forencich	00dc50826d	Update example designs	2018-10-24 01:03:44 -07:00
Alex Forencich	e4672915e6	Update testbenches to use instances()	2018-06-13 22:43:11 -07:00
Alex Forencich	298ae4defa	Update MAC module instantiation	2018-06-13 22:16:02 -07:00
Alex Forencich	c31757552b	Add crosspoint design	2018-05-31 16:27:56 -07:00
Alex Forencich	855b593ce5	Minor updates to 10G example designs	2018-05-31 16:05:41 -07:00
Alex Forencich	0fd157964a	Happy new year	2018-02-26 12:50:51 -08:00
Alex Forencich	bd27156f35	AXI stream updates	2018-02-26 00:08:08 -08:00
Alex Forencich	0fc986041e	Fix example design LED logic	2017-05-19 17:44:29 -07:00
Alex Forencich	9b2ac9dfc1	Happy new year	2017-05-18 13:47:45 -07:00
Alex Forencich	270641b7a3	Update UDP modules and example designs to utilize UDP checksum modules	2016-09-30 22:15:21 -07:00
Alex Forencich	88150c9d5f	Update and rework endpoints, update testbenches	2016-09-13 15:24:02 -07:00
Alex Forencich	47ca9a8725	Replace eth_crc modules for generic lfsr module	2016-06-28 17:31:58 -07:00
Alex Forencich	b1dca3b57a	Add missing declaration	2016-02-12 18:27:54 -08:00
Alex Forencich	f36256c541	Add 10G reference design for HXT100G	2016-01-25 19:11:42 -08:00