20 Commits

Author	SHA1	Message	Date
Alex Forencich	90959b8795	Add default_nettype none and resetall directives	2021-10-20 17:49:30 -07:00
Alex Forencich	824e9fc758	Resize registers	2021-10-02 00:46:21 -07:00
Alex Forencich	d0705fea9b	Minor optimizations to completion TLP size computation logic	2021-10-01 13:00:22 -07:00
Alex Forencich	c044898ec4	One AXI read burst per completion TLP	2021-10-01 00:20:29 -07:00
Alex Forencich	c47f3f5280	AT is reserved in completions	2021-08-06 01:49:47 -07:00
Alex Forencich	3e03b20bc7	Properly handle zero-length PCIe read and write operations	2021-07-24 01:13:25 -07:00
Alex Forencich	f8bc6c31e5	Update AXI master modules to support 512 bit interface	2019-10-14 16:20:46 -07:00
Alex Forencich	a92722173a	Handle ultrascale plus interface widths	2019-10-04 16:29:11 -07:00
Alex Forencich	1b98af9364	Fix part-select range	2019-10-01 22:00:03 -07:00
Alex Forencich	e97e4ad423	Parametrize tuser signal widths	2019-09-26 23:30:03 -07:00
Alex Forencich	f518aec219	Include instance names in error messages	2019-07-25 16:38:54 -07:00
Alex Forencich	c75f29c648	Add parameter documentation	2019-07-24 18:01:13 -07:00
Alex Forencich	5db9cddf6e	Reorganize and simplify burst length computation code	2018-11-29 15:20:01 -08:00
Alex Forencich	008a7167c7	Add AXI_MAX_BURST_SIZE parameter to PCIe AXI master	2018-11-26 18:03:54 -08:00
Alex Forencich	d81ee9487a	Add some more comments	2018-11-26 15:56:13 -08:00
Alex Forencich	24f709573c	Only store on valid transfer in	2018-11-26 13:18:38 -08:00
Alex Forencich	1dcc091201	Adjustments for 64 bit datapath	2018-11-26 13:17:41 -08:00
Alex Forencich	a6809a6b57	Use constants instead of magic numbers	2018-11-26 13:07:50 -08:00
Alex Forencich	c3d4aeda48	Use logical operators	2018-11-08 23:36:05 -08:00
Alex Forencich	b3ebb04491	Add Ultrascale PCIe AXI master read module and testbenches	2018-10-23 20:50:48 -07:00