Alex Forencich
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940c1210c1
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Convert arbitrated mux to verilog parametrized arbitrated mux
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2018-10-24 13:49:17 -07:00 |
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Alex Forencich
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fe77db822d
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Convert generated crosspoint to verilog parametrized crosspoint
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2018-10-24 13:44:39 -07:00 |
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Alex Forencich
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553547f661
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Fix test naming
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2018-09-09 13:52:13 -07:00 |
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Alex Forencich
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becfbf4425
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When pausing the AXI stream model, do not drop tvalid if it is asserted and waiting for tready to be asserted
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2018-08-15 00:11:39 -07:00 |
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Alex Forencich
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8e5ec36ced
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Optimize axis_arb_mux and improve latency
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2018-08-09 18:40:50 -07:00 |
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Alex Forencich
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3063bba54b
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Update testbenches to use wait
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2018-07-02 16:19:35 -07:00 |
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Alex Forencich
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9390c3639b
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More endpoint updates
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2018-07-02 14:13:47 -07:00 |
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Alex Forencich
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268d011b89
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Add wait method to sink
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2018-06-30 00:21:26 -07:00 |
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Alex Forencich
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2ebffeb223
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Be more pythonic
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2018-06-30 00:21:02 -07:00 |
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Alex Forencich
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c5837daa2f
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Update testbenches to use instances()
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2018-06-13 22:26:10 -07:00 |
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Alex Forencich
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5df7efe516
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Happy new year
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2018-02-26 12:25:20 -08:00 |
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Alex Forencich
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c33985d7ba
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Remove extraneous parameter
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2017-11-21 08:54:21 -08:00 |
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Alex Forencich
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b00eaf4d3c
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Add tkeep signal and update testbench for stat counter
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2017-11-21 00:17:42 -08:00 |
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Alex Forencich
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ad0e3e1eb5
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Whitespace fixes and testbench update for frame joiner
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2017-11-21 00:16:15 -08:00 |
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Alex Forencich
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a1a6d523e3
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Update FIFO instances and testbenches for COBS encoder and decoder
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2017-11-21 00:14:26 -08:00 |
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Alex Forencich
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0edafd58ac
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream tap
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2017-11-20 23:45:34 -08:00 |
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Alex Forencich
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4ef4ef2622
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL register
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2017-11-20 21:34:25 -08:00 |
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Alex Forencich
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b0d7820f5b
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL FIFO
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2017-11-20 21:32:46 -08:00 |
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Alex Forencich
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d16f19f67e
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream rate limiter
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2017-11-20 21:31:41 -08:00 |
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Alex Forencich
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772e433ee9
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame length adjuster
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2017-11-20 21:30:26 -08:00 |
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Alex Forencich
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de590517a9
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream switch
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2017-11-20 20:17:20 -08:00 |
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Alex Forencich
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91a7169f46
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream crosspoint
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2017-11-20 20:16:21 -08:00 |
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Alex Forencich
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496c63bd1c
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream arbitrated mux
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2017-11-20 20:15:08 -08:00 |
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Alex Forencich
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57e700f802
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream demux
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2017-11-20 20:14:20 -08:00 |
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Alex Forencich
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9e4aa38750
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream mux
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2017-11-20 20:13:53 -08:00 |
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Alex Forencich
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d50c767482
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream adapter
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2017-11-20 20:12:43 -08:00 |
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Alex Forencich
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fdb881719c
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async frame FIFO
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2017-11-20 20:12:02 -08:00 |
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Alex Forencich
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1c7362c717
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame FIFO
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2017-11-20 20:11:44 -08:00 |
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Alex Forencich
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7d237f55c1
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async FIFO
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2017-11-20 20:11:08 -08:00 |
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Alex Forencich
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190d75df9d
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream FIFO
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2017-11-20 20:10:41 -08:00 |
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Alex Forencich
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a5524287ca
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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream register
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2017-11-20 20:09:48 -08:00 |
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Alex Forencich
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a0b21db746
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Improve checks in axis_ep
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2017-11-20 15:43:54 -08:00 |
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Alex Forencich
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c9cc9006a3
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Add last_cycle_user parameter to axis_ep
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2017-11-20 15:43:32 -08:00 |
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Alex Forencich
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7dc58e5d49
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Add tid signal to axis_ep
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2017-11-12 18:17:33 -08:00 |
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Alex Forencich
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3e2b94f6c7
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Return False instead of None for mismatched objects
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2017-05-18 13:52:05 -07:00 |
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Alex Forencich
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3b0cfbbfed
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Use extend instead of for loop
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2017-05-18 13:35:42 -07:00 |
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Alex Forencich
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aebe0549dd
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Happy new year
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2017-05-18 13:35:11 -07:00 |
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Alex Forencich
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5fa36eeaa7
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Rework endpoints, update testbenches
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2016-09-12 13:38:34 -07:00 |
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Alex Forencich
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e989f15ff4
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Remove some test cases
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2016-08-22 08:17:26 -07:00 |
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Alex Forencich
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24f7aee8b2
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Add COBS encoder and decoder modules and testbench
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2016-08-21 20:03:54 -07:00 |
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Alex Forencich
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e6d78b7ca7
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Add extra testbench delay
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2016-08-04 18:03:24 -07:00 |
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Alex Forencich
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06bfa1944c
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Add AXI stream switch module, generator script, and testbench
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2016-07-25 13:12:10 -07:00 |
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Alex Forencich
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5fe35a79d2
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Add tdest support to axis_ep
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2016-07-25 11:28:35 -07:00 |
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Alex Forencich
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be4034071b
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Happy new year
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2016-01-05 00:24:20 -08:00 |
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Alex Forencich
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364b537312
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Synchronize status signals for both clock domains in async frame FIFO
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2015-10-09 15:14:54 -07:00 |
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Alex Forencich
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30a35c3d73
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Convert async fifo to common reset
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2015-10-08 12:52:51 -07:00 |
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Alex Forencich
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120f86f4cf
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Add SRL FIFO reset tests
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2015-07-13 23:15:39 -07:00 |
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Alex Forencich
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516c50d786
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Add FIFO reset tests
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2015-07-09 11:13:25 -07:00 |
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Alex Forencich
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87fe1a561f
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Add AXI stream tap modules
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2015-06-22 14:56:56 -07:00 |
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Alex Forencich
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c15761068a
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Add AXI stream frame length adjust modules
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2015-06-05 17:04:10 -07:00 |
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