Alex Forencich
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eb990643f2
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fpga/mqnic: various minor cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-12 17:12:07 -07:00 |
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Alex Forencich
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5f1e74b0e1
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Add PROJECT variable, remove multiple stem matches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-11 13:33:09 -07:00 |
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Alex Forencich
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7017e7d49b
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Explicitly set top module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-11 12:29:01 -07:00 |
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Alex Forencich
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ceb6a9ca06
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Update clean target
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-11 12:26:39 -07:00 |
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Alex Forencich
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9c98f12392
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Write debug probes file alongside bit file
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-10 23:37:54 -07:00 |
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Alex Forencich
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9628401780
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Normalize output file location
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-10 21:47:53 -07:00 |
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Alex Forencich
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caf2a0993b
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fpga: Output hierarchical utilization reports
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-06 21:17:25 -07:00 |
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Alex Forencich
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d7904b8007
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fpga: Add support for IRQ rate limiting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-09-04 15:24:40 -07:00 |
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Alex Forencich
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1486da601f
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fpga: Add clock period parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-09-04 12:03:35 -07:00 |
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Alex Forencich
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81648cf85b
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fpga/mqnic: Clean up PCIe DMA IF flow control connections
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-03 23:04:05 -07:00 |
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Alex Forencich
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c76e152804
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Rename cmac_ts_insert to mac_ts_insert
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-18 22:27:27 -07:00 |
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Alex Forencich
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e47175e5f2
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Add 100G mqnic design for BittWare 250-SoC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-18 22:26:22 -07:00 |
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