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mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00

11 Commits

Author SHA1 Message Date
Alex Forencich
eb990643f2 fpga/mqnic: various minor cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-10-12 17:12:07 -07:00
Alex Forencich
d7904b8007 fpga: Add support for IRQ rate limiting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-09-04 15:24:40 -07:00
Alex Forencich
1486da601f fpga: Add clock period parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-09-04 12:03:35 -07:00
Alex Forencich
6c6648f114 fpga/mqnic: Add RAM inference directive to Intel designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-08-05 16:27:29 -07:00
Alex Forencich
81648cf85b fpga/mqnic: Clean up PCIe DMA IF flow control connections
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-08-03 23:04:05 -07:00
Alex Forencich
3f57c2143b fpga/mqnic: PCIe interface updates
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-08-03 12:28:49 -07:00
Alex Forencich
607ce498cf fpga/mqnic: Update PCIe DMA settings on Intel designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-08-03 00:42:19 -07:00
Alex Forencich
4bcac62c2a fpga/mqnic: Disable PTP on 100G E-tile designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-08-03 00:41:53 -07:00
Alex Forencich
ec17500a66 Add 100G mqnic design for DE10-Agilex
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-21 18:49:35 -07:00
Alex Forencich
ae5a029720 Update PCIe model configuration
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-21 18:49:17 -07:00
Alex Forencich
03a49d7bc6 Add 25G mqnic design for DE10-Agilex
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-19 23:43:22 -07:00