Alex Forencich
|
eb990643f2
|
fpga/mqnic: various minor cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-12 17:12:07 -07:00 |
|
Alex Forencich
|
5f1e74b0e1
|
Add PROJECT variable, remove multiple stem matches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-11 13:33:09 -07:00 |
|
Alex Forencich
|
7017e7d49b
|
Explicitly set top module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-11 12:29:01 -07:00 |
|
Alex Forencich
|
ceb6a9ca06
|
Update clean target
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-11 12:26:39 -07:00 |
|
Alex Forencich
|
9c98f12392
|
Write debug probes file alongside bit file
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-10 23:37:54 -07:00 |
|
Alex Forencich
|
9628401780
|
Normalize output file location
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-10 21:47:53 -07:00 |
|
Alex Forencich
|
caf2a0993b
|
fpga: Output hierarchical utilization reports
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-06 21:17:25 -07:00 |
|
Alex Forencich
|
d7904b8007
|
fpga: Add support for IRQ rate limiting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-09-04 15:24:40 -07:00 |
|
Alex Forencich
|
1486da601f
|
fpga: Add clock period parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-09-04 12:03:35 -07:00 |
|
Alex Forencich
|
81648cf85b
|
fpga/mqnic: Clean up PCIe DMA IF flow control connections
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-08-03 23:04:05 -07:00 |
|
Alex Forencich
|
0afe9be906
|
fpga/mqnic/VCU108: Update VCU108 design to support 25G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-26 23:26:11 -07:00 |
|