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377 Commits

Author SHA1 Message Date
Alex Forencich
1fc991fc05 Convert fb2CG designs to use common core modules 2021-08-31 21:33:49 -07:00
Alex Forencich
bd3fa6abfd Update vivado.mk 2021-08-31 20:03:33 -07:00
Alex Forencich
d46cb16dbf Add scheduler block 2021-08-30 01:28:55 -07:00
Alex Forencich
f71d28c6d8 Normalize RAM size and max frame size 2021-08-20 21:18:44 -07:00
Alex Forencich
4ceefa376a Normalize FIFO size to 32K 2021-08-20 21:17:41 -07:00
Alex Forencich
34150323df Remove obsolete packet table size parameters 2021-08-20 18:15:06 -07:00
Alex Forencich
84e19ca305 Update file lists 2021-08-16 18:12:19 -07:00
Alex Forencich
38f766646b Connect flow control signals to pcie_us_if 2021-08-12 00:05:43 -07:00
Alex Forencich
6517d43ee7 Add missing connection 2021-08-11 23:52:44 -07:00
Alex Forencich
a19474f9dd Use AXI lite crossbar 2021-08-11 01:31:34 -07:00
Alex Forencich
3e489fde27 Fix instance name 2021-08-04 12:37:13 -07:00
Alex Forencich
49aa27d1c5 Add placement constraints for AU50 2021-08-04 01:23:22 -07:00
Alex Forencich
0b65a1271a Use new PCIe DMA modules 2021-08-04 01:20:57 -07:00
Alex Forencich
e0e34a9f0d Update designs for PCIe module changes 2021-08-02 23:04:52 -07:00
Alex Forencich
4ed99c6f87 Remove CMS IP version number 2021-07-03 00:09:10 -07:00
Alex Forencich
0a7f1ccbbe Remove string parameters 2021-06-02 18:18:23 -07:00
Alex Forencich
15cb21dbd1 Reorganize timing constraints 2021-05-20 15:24:01 -07:00
Alex Forencich
7b2a0a1aed Update testbenches 2021-04-28 20:54:44 -07:00
Alex Forencich
0916fb6686 Enable PTP on NetFPGA SUME 2021-04-01 21:58:32 -07:00
Alex Forencich
1bb5d8ab56 Add PTP support at 100G on VCU118 2021-04-01 18:02:58 -07:00
Alex Forencich
cf6e8bba99 Add PTP support at 100G on ADM-PCIE-9V3 2021-04-01 18:02:26 -07:00
Alex Forencich
d4b009b6d2 Add PTP support at 100G on VCU1525 2021-04-01 17:25:57 -07:00
Alex Forencich
2d20ee2807 Add PTP support at 100G on Alveo U50 2021-04-01 17:08:06 -07:00
Alex Forencich
275c0e98e9 Add PTP support at 100G on Alveo U250 2021-04-01 16:53:00 -07:00
Alex Forencich
77bb4b9dd8 Add PTP support at 100G on Alveo U200 2021-04-01 16:52:00 -07:00
Alex Forencich
2975e075d4 Add PTP support at 100G on Alveo U280 2021-04-01 16:31:23 -07:00
Alex Forencich
31c902685a Add PTP support at 100G on fb2CG@KU15P 2021-04-01 16:29:52 -07:00
Alex Forencich
c7896bef92 Use correct assignment type 2021-03-30 21:50:25 -07:00
Alex Forencich
2afbd1f15b Enable PTP in 25G designs 2021-03-30 18:53:52 -07:00
Alex Forencich
1aeeb0bbe2 Update designs for PTP CDC and Ethernet MAC module changes 2021-03-30 16:41:31 -07:00
Alex Forencich
32abea89fa Update testbenches 2021-03-06 20:30:25 -08:00
Alex Forencich
d416e9f7fa Roll back PCIe tag count to 64 2021-03-05 14:04:52 -08:00
Alex Forencich
705133bf7a Add SPI interface to Gecko BMC on fb2CG@KU15P 2021-03-04 22:34:52 -08:00
Alex Forencich
a644d6dd3f Update Vivado makefiles 2021-03-01 23:05:37 -08:00
Alex Forencich
d0b19efce5 Reconcile PCIe changes 2021-03-01 00:25:15 -08:00
Alex Forencich
a3c104f7dd Connect write done signals 2021-02-24 15:07:26 -08:00
Alex Forencich
4b3d153cbd Add placement constraints for fb2CG@KU15P 2021-02-23 02:33:37 -08:00
Alex Forencich
2779087de9 Constrain DMA muxes to same SLR 2021-02-23 02:17:10 -08:00
Alex Forencich
ceebb9f20e Add more PCIe-related components to PCIe pblock 2021-02-23 00:55:05 -08:00
Alex Forencich
6ab66ed347 Fix signal name in xdc 2021-02-14 15:08:13 -08:00
Alex Forencich
ea093b0126 More XDC cleanup 2021-02-06 15:15:05 -08:00
Alex Forencich
46149bef3f Update ZCU106 XDC 2021-02-05 22:22:25 -08:00
Alex Forencich
24d179dd4a VCU118 XDC cleanup 2021-02-05 22:14:00 -08:00
Alex Forencich
0c1acadbfa Enable termination on LVDS clock input 2021-02-05 22:12:59 -08:00
Alex Forencich
1d7dc703b5 Add cfgmclk timing constraints, rework reset connections 2021-02-05 18:00:56 -08:00
Alex Forencich
b16fe8f7e7 More XDC clean up, add IO delay constraints for low speed IO 2021-02-05 16:08:23 -08:00
Alex Forencich
89d7042aeb Add CMS IP to all Alveo designs 2021-01-31 14:17:49 -08:00
Alex Forencich
722bd929b8 Placement updates 2021-01-31 12:48:49 -08:00
Alex Forencich
151ed7e179 Add extra reset registers 2021-01-31 11:10:03 -08:00
Alex Forencich
1248ca1a2e Add power budget to Alveo XDC files 2021-01-29 15:44:15 -08:00