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2,918 Commits 1 Branch 0 Tags
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213 Commits

Author SHA1 Message Date
Alex Forencich
95af2136b1 fpga/common: Increase event FIFO size 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-14 01:03:19 -07:00
Alex Forencich
bb158d568f Add RX indirection table 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-10 15:05:32 -07:00
Alex Forencich
30379cd8a3 Add phase tag to events and completions to avoid queue pointer reads 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-06 20:43:13 -07:00
Alex Forencich
54b3c8199c fpga/common: Add re-arm bit in tail pointer register in completion queue manager 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-06 16:58:50 -07:00
Alex Forencich
394dc2d723 fpga/common: Add phase bit to queue managers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-05 01:38:46 -07:00
Alex Forencich
ca07a23afc fpga/common: Add extra non-ASYNC_REG registers on transceiver resets to permit replication 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-24 21:34:42 -08:00
Alex Forencich
0f86ea9bb1 fpga/common: Remove unnecessary reset from clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-24 21:32:30 -08:00
Alex Forencich
86e87c7c3b Fix PTP clock offset ns field width 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 15:47:47 -08:00
Alex Forencich
6c58e950d3 fpga/mqnic: Add DRAM interface module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-19 16:47:02 -08:00
Alex Forencich
6d4373ec97 fpga/common: Rework stats counter to use pipeline and infer URAM 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-01 17:15:56 -08:00
Alex Forencich
bf7cf3fef9 Add CMAC wrapper 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-09 20:58:30 -08:00
Alex Forencich
f6262c3606 fpga/mqnic: Update FIFO parameter naming 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 23:57:50 -07:00
Alex Forencich
b19ff209da fpga/common: More parameter cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 23:30:17 -07:00
Alex Forencich
d3942da875 fpga: Add clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 19:45:02 -07:00
Alex Forencich
d0cc106783 fpga: Remove redundant RX_RSS_ENABLE parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-13 17:10:25 -07:00
Alex Forencich
941288e926 fpga/common: Add AXI interfaces for DDR and HBM to core logic and application section 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 17:12:23 -07:00
Alex Forencich
fe37e4a4bb fpga/common: Use correct parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-06 21:15:26 -07:00
Alex Forencich
56fe10f27d fpga/common: Fix lost TX request status issue in transmit engine 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-21 15:20:27 -07:00
Alex Forencich
efbeecde35 fpga/common: Clean up parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-21 15:19:49 -07:00
Alex Forencich
4b8aaea5c1 fpga/common: Add skid buffer to TX/RX engine DMA descriptor outputs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-20 21:50:58 -07:00
Alex Forencich
d7904b8007 fpga: Add support for IRQ rate limiting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 15:24:40 -07:00
Alex Forencich
1486da601f fpga: Add clock period parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 12:03:35 -07:00
Alex Forencich
803841421e fpga/common: Fix tied-off net name 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-03 18:34:42 -07:00
Alex Forencich
44c81574d7 fpga/common: Add backpressure to completion queue manager event/interrupt output 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-16 18:51:53 -07:00
Alex Forencich
1c1db788ac fpga/common: Fix incorrect parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-08 13:10:05 -07:00
Alex Forencich
cc99484d99 fpga/common: add missing parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 23:04:23 -07:00
Alex Forencich
81648cf85b fpga/mqnic: Clean up PCIe DMA IF flow control connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 23:04:05 -07:00
Alex Forencich
3f57c2143b fpga/mqnic: PCIe interface updates 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 12:28:49 -07:00
Alex Forencich
46a88e64c5 mqnic/common: Update UltraScale shim instance 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-26 14:05:11 -07:00
Alex Forencich
549e60bdd1 Only use avst_empty at end of frame 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 23:00:09 -07:00
Alex Forencich
03a49d7bc6 Add 25G mqnic design for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-19 23:43:22 -07:00
Alex Forencich
4b6a96d5ee Add mqnic core logic for Intel P-Tile 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 23:15:54 -07:00
Alex Forencich
c76e152804 Rename cmac_ts_insert to mac_ts_insert 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:27:27 -07:00
Alex Forencich
ef5b2449dc Add stretched PTP PPS output 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:58 -07:00
Alex Forencich
676f3edd2d Add TX PTP clock to port map module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:39 -07:00
Alex Forencich
e0d92172d3 Separate PTP TX clock input 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:24:41 -07:00
Alex Forencich
6b0df7f33f Rework RX request generation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-09 14:43:39 -07:00
Alex Forencich
729c3a0458 Update for PCIe shim changes, enable TLP straddling on US/US+ devices, and use 256 tags on US+ devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-08 22:07:18 -07:00
Alex Forencich
c95e8f70f2 Update PCIe TLP interface parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 14:31:10 -07:00
Alex Forencich
21b0f014a5 Switch to MSI-X 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:58:29 -07:00
Alex Forencich
ed2d34153d Use PHY rx_status signal for link status detection 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-17 00:46:05 -07:00
Alex Forencich
2b33698f9b Fix alignment 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 13:25:13 -07:00
Alex Forencich
827cb1ea1d Pipeline arbitration delay in muxes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:35:39 -07:00
Alex Forencich
01aa6a885b Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:32:28 -07:00
Alex Forencich
a020225304 Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:30:14 -07:00
Alex Forencich
835f0d38f0 Update PTP subsystem to use separate clock for improved stability 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-06 17:46:16 -07:00
Alex Forencich
18d5c325bf Fix CMAC RX PTP timestamps 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-05 23:21:11 -07:00
Alex Forencich
c2fea3a616 Add port register blocks with support for PHY link status reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-04 09:03:37 -07:00
Alex Forencich
cfdd6f5455 Decouple transmit completion handling from PTP timestamping 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-01 17:41:47 -07:00
Alex Forencich
53f3547ef5 Rework hierarchy to move port-specific logic out of mqnic_core and into mqnic_interface and new port-level modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-29 14:32:57 -07:00