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6 Commits

Author SHA1 Message Date
Alex Forencich
786e971f40 Remove separate memory read register (it causes ISE to crash, and is not necessary for URAM inference) 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-29 23:54:17 -08:00
Alex Forencich
46bd4302de Update async FIFO timing constraints to handle clocks from OOC IP that are not constrained during synthesis 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-08 18:49:21 -08:00
Alex Forencich
ed6130575d Update async FIFO timing constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 23:27:39 -07:00
Alex Forencich
10e24cc5b1 Fix timing constraints 2021-10-13 18:07:45 -07:00
Alex Forencich
4f1eabab17 Split async FIFO resets 2021-10-13 14:05:13 -07:00
Alex Forencich
e9f7723312 Reorganize timing constraints 2021-05-16 23:28:00 -07:00