8 Commits

Author	SHA1	Message	Date
Alex Forencich	967aa8c2f3	Mask instead of barrel shift	2019-06-21 20:38:09 -07:00
Alex Forencich	435f0b8749	Timing optimization of wstrb	2019-06-21 12:04:58 -07:00
Alex Forencich	834d6a4b2d	Improve timing for unaligned operations (shift_axis_extra_cycle)	2019-06-15 21:27:41 -07:00
Alex Forencich	f128190130	Ensure transfer is terminated at the end of the input frame	2019-03-13 14:48:05 -07:00
Alex Forencich	e71a62e6a1	Fix backpressure issue	2019-03-07 17:45:25 -08:00
Alex Forencich	04dd6a34d7	Fix combinatorial loop	2019-02-20 18:48:27 -08:00
Alex Forencich	7654d874ae	Fix out of range access due to off by one error	2019-02-11 19:30:57 -08:00
Alex Forencich	41f8667310	Add AXI write DMA module and testbenches	2018-12-27 14:15:51 -08:00